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0015.register allocation-graph-coloring

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sean chen
sean chen

The document discusses register allocation techniques used by compilers to optimize code generation. It describes how register allocation works by constructing a register interference graph and using graph coloring algorithms to assign temporaries to a limited number of machine registers. When graph coloring fails to find a solution, spilling of temporaries is used to reduce interferences and allow coloring. Cache optimization is also briefly covered.

EducaçãoTecnologia
1 de 37
Register Allocation (via graph coloring)
Lecture Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Memory Hierarchy Registers 1 cycle 256-8000 bytes Cache 3 cycles 256k-1M Main memory 20-100 cycles 32M-1G Disk 0.5-5M cycles 4G-1T
Managing the Memory Hierarchy ,[object Object],[object Object],[object Object],[object Object]
Current Trends to manage memory hierarchy ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
The Register Allocation Problem ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
History of register allocation problem ,[object Object],[object Object],[object Object],[object Object],[object Object]
An Example of register allocation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Basic Register Allocation Idea ,[object Object],[object Object],[object Object],[object Object]
Algorithm to minimize the number of registers: Part I ,[object Object],a f e d c b {a,b} not included in any subset a := b + c d := -a e := d + f f := 2 * e b := d + e e := e - 1 b := f + c {b} {c,e} {b} {c,f} {c,f} {b,c,e,f} {c,d,e,f} {b,c,f} {c,d,f} {a,c,f}
The Register Interference Graph ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Register Interference Graph. Example. ,[object Object],a f e d c b ,[object Object],[object Object],a := b + c d := -a e := d + f f := 2 * e b := d + e e := e - 1 b := f + c
Register Interference Graph . Properties. ,[object Object],[object Object],[object Object]
Graph Coloring. Definitions. ,[object Object],[object Object]
Register Allocation Through Graph Coloring ,[object Object],[object Object],[object Object],[object Object],Register Interference Graph
Graph Coloring. Example. ,[object Object],[object Object],[object Object],a f e d c b r 4 r 1 r 2 r 3 r 2 r 3
Graph Coloring. Example. ,[object Object],r 2 := r 3 + r 4 r 3 := -r 2 r 2 := r 3 + r 1 r 1 := 2 * r 2 r 3 := r 3 + r 2 r 2 := r 2 - 1 r 3 := r 1 + r 4
Computing Graph Colorings ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Graph Coloring Heuristic ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Graph Coloring Heuristic ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Graph Coloring Example (1) ,[object Object],a f e d c b ,[object Object],Stack: {}
Graph Coloring Example (2) ,[object Object],f e c b Stack: { d , a }
Graph Coloring Example (2) ,[object Object],r 4 r 1 r 2 r 3 r 2 r 3 b a e c f d
What if the Heuristic Fails? ,[object Object],[object Object],a f e d c b
What if the Heuristic Fails? ,[object Object],[object Object],[object Object],[object Object],f e d c b
What if the Heuristic Fails? ,[object Object],[object Object],e d c b
What if the Heuristic Fails? ,[object Object],[object Object],? f e d c b r 3 r 1 r 2 r 3
Spilling ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Spilling. Example. ,[object Object],a := b + c d := -a f := load fa e := d + f f := 2 * e store f, fa b := d + e e := e - 1 f := load fa b := f + c
Recomputing Liveness Information ,[object Object],a := b + c d := -a f := load fa e := d + f f := 2 * e store f, fa b := d + e e := e - 1 f := load fa b := f + c {b} {c,e} {b} {c,f} {c,f} {b,c,e,f} {c,d,e,f} {b,c,f} {c,d,f} {a,c,f} {c,d,f} {c,f} {c,f}
Recomputing Liveness Information ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Recompute RIG After Spilling ,[object Object],[object Object],[object Object],a f e d c b
Spilling (Cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Caches ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Cache Optimization ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Cache Optimization (Cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Conclusions ,[object Object],[object Object],[object Object],[object Object],[object Object]

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0015.register allocation-graph-coloring

  • 1. Register Allocation (via graph coloring)
  • 2.
  • 3. The Memory Hierarchy Registers 1 cycle 256-8000 bytes Cache 3 cycles 256k-1M Main memory 20-100 cycles 32M-1G Disk 0.5-5M cycles 4G-1T
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