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FPGA Platform with DSP capabilities for industrial and
                        educational Applications-1
                                 FPDA-1
                                                 J. Boutsen, V. Claes, P. Hilven, K. Stevens, F. Appaerts
                             XIOS Hogeschool Limburg, Universitaire Campus, Agoralaan, Gebouw H, B-3590 Diepenbeek, Belgium
                                         Futher information: jan.boutsen@xios.be ; vincent.claes@xios.be ; patrick.hilven@xios.be ; kenny.stevens@xios.be ; frank.appaerts@xios.be



Introduction
For our subsections within electronics it is important to examine new techniques and to update our knowledge in the domain of FPGA (Field Programming Gate Array) embedded
system development. The aim of our FPDA project is to find out in practice which developing environments are suitable at this moment in order to develop an FPGA embedded
system in a very short span of time and make it ready for production.With this project we expect a more intensive interaction to grow between our institutes for higher education,
knowledge centres and Flemish small and medium-sized companies, already active or wanting to be so in the field of hardware and software development for FPGA embedded
systems.This project is backed up by a multidisciplinary team with a combined know-how and experience in electronics design, programmable logics and system software.


Research                                              Development flow for FPGA                                                                                                                                               HDL development platform


                                                      Create Code/                          VHDL RTL
          Plan& Budget
                                                       Schematic                            Simulation


                                                                                                                                                                   ModelSim SE 6.0a.lnk
                                                                                                                                      Xilinx Platform Studio.lnk
           Implement
                                                                                                                                                                                                                                                                I/O Blocks (IOB)
                                                         Functional                           Synthesize
               Translate                                 Simulation                        to create netlist
                                                                                                                                                                         HDL +
                                                                                                                                               HDL
                                                                                                                                                                       TESTBENCH                                                                                Configurable
                 Map
                                                                                                                                                                                                                                                                Logic Blocks
                                                                                                                                                                                                                                                                   (CLB)
             Place & Route


                                                                                                                                        Xilinx ISE 7.1i.lnk                                                                                                    Programmable
                                                                                                                                                                                                                                                                interconnect
                                                            Timing
            Attain Timing                                                                         Create
                                                          Simulation
               Closure                                                                           BIT File




                                                                             Mathworks development platform                                                                                              Mixed-Signal development platform

                                                                                                                                                                        TYPICAL SYSTEM

                                                                                                                                                                         System Memory                         Cache Memory      NV Storage
                                                                                                                                                                         System Memory                         Cache Memory      NV Storage
                                                                                                                                                                              DRAM                                 SRAM             FLASH
                                                                                                                                                                             DRAM                                 SRAM             FLASH


                                                                                                                                                                                              MPU / /MCU
                                                                                                                                                                                              MPU MCU                    FPGA / /ASIC
                                                                                                                                                                                                                          FPGA ASIC
                                                                                                               ModelSim SE 6.0a.lnk


                                                                                                                                                                             Analog                   Power               Clock         Discrete
                                                                                                                                                                            Analog                   Power               Clock          Discrete
                                                                                                                                                                            Interface              Management          Management        Analog
                                                                                                                     HDL +                                                 Interface               Management          Management       Analog
                                                                                                                   TESTBENCH



                                                                                                                                                                                            One-chip solution                                      Industry-standard, 32-bit architecture
                                                                                                                                                                        Retains programmed when powered off                                        Extensive software and tools ecosystem
                                                                                                                                                                                                                                  SOFT
                                                                                                                                                                                        350 MHz performance                                        The only Soft ARM7 FPGA Implementation
                                                                                                                                                                                                                                  ARM7


                                                                                                                                                                                                                        FPGA
                                                                                                                                                                                                       12-bit ADC                                  Up to 8 Mbits
                                                                                                                                                                        Voltage, Current and temperature monitors                                  Configurable 8, 16 and 32-bit data paths
                                                                                                                                                                                               12-volt tolerant I/O                                High-performance up to 10ns access


                                                                                                                                                                                                                       ANALOG      FLASH
                                                                                                                                                                                                                      ANALOG      FLASH




              Evolution of Embedded system platforms                                                                                                                                                                  LabVIEW development platform
                                                             Few applications           Many applications
       1 algorithm            1 application

                                                                                                               ?




                                                                            Application mapping
                                     +            >



                                     -    *




                                         FPGA                           RTOS & Middleware

                                              B
                               MEM
                                              U
                                              S
                                                                 MEM
                               CPU
             ASIC
                                                                MEM
                                                               MEM
                                                                        B
                                                               MEM
                                                                        U
                                                                        S
                                                               CPU
                                                                CPU
                               (ASIP) SoC                        CPU
                                                                  CPU




                                                            Multi-Processor        Re-configurable SoC platform
                                                               Platform




Conclusion
There is a wide offer of developing environments nowadays for an FPGA Embedded system. Unlike some years ago when there used to be quite a range of developing
environments with software and hardware components of their own, this market now rather seems to focus on generating hardware-independent and synthesizable HDL. Graphic
developing environments are increasing in scope so much so that the ‘developer’ need not be a software or hardware specialist at all. The result of this trend is that companies
wanting to use an FPGA as an embedded system are likely to overcome their initial hesitation. Despite this positive evolution we have noticed, throughout our research, some less
favourable tendencies on behalf of the developer. Mutual exchangeability between developing environments of different manufacturers is not quite unproblematic. New software
versions and service packs succeed one another as quickly as lightning. The usage of FPGA as an Embedded system and the graphic developing environment presented for that
purpose enable the software and hardware developers to market a reliable product within a short lapse of time.

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FPDA-1 Project Poster

  • 1. FPGA Platform with DSP capabilities for industrial and educational Applications-1 FPDA-1 J. Boutsen, V. Claes, P. Hilven, K. Stevens, F. Appaerts XIOS Hogeschool Limburg, Universitaire Campus, Agoralaan, Gebouw H, B-3590 Diepenbeek, Belgium Futher information: jan.boutsen@xios.be ; vincent.claes@xios.be ; patrick.hilven@xios.be ; kenny.stevens@xios.be ; frank.appaerts@xios.be Introduction For our subsections within electronics it is important to examine new techniques and to update our knowledge in the domain of FPGA (Field Programming Gate Array) embedded system development. The aim of our FPDA project is to find out in practice which developing environments are suitable at this moment in order to develop an FPGA embedded system in a very short span of time and make it ready for production.With this project we expect a more intensive interaction to grow between our institutes for higher education, knowledge centres and Flemish small and medium-sized companies, already active or wanting to be so in the field of hardware and software development for FPGA embedded systems.This project is backed up by a multidisciplinary team with a combined know-how and experience in electronics design, programmable logics and system software. Research Development flow for FPGA HDL development platform Create Code/ VHDL RTL Plan& Budget Schematic Simulation ModelSim SE 6.0a.lnk Xilinx Platform Studio.lnk Implement I/O Blocks (IOB) Functional Synthesize Translate Simulation to create netlist HDL + HDL TESTBENCH Configurable Map Logic Blocks (CLB) Place & Route Xilinx ISE 7.1i.lnk Programmable interconnect Timing Attain Timing Create Simulation Closure BIT File Mathworks development platform Mixed-Signal development platform TYPICAL SYSTEM System Memory Cache Memory NV Storage System Memory Cache Memory NV Storage DRAM SRAM FLASH DRAM SRAM FLASH MPU / /MCU MPU MCU FPGA / /ASIC FPGA ASIC ModelSim SE 6.0a.lnk Analog Power Clock Discrete Analog Power Clock Discrete Interface Management Management Analog HDL + Interface Management Management Analog TESTBENCH One-chip solution Industry-standard, 32-bit architecture Retains programmed when powered off Extensive software and tools ecosystem SOFT 350 MHz performance The only Soft ARM7 FPGA Implementation ARM7 FPGA 12-bit ADC Up to 8 Mbits Voltage, Current and temperature monitors Configurable 8, 16 and 32-bit data paths 12-volt tolerant I/O High-performance up to 10ns access ANALOG FLASH ANALOG FLASH Evolution of Embedded system platforms LabVIEW development platform Few applications Many applications 1 algorithm 1 application ? Application mapping + > - * FPGA RTOS & Middleware B MEM U S MEM CPU ASIC MEM MEM B MEM U S CPU CPU (ASIP) SoC CPU CPU Multi-Processor Re-configurable SoC platform Platform Conclusion There is a wide offer of developing environments nowadays for an FPGA Embedded system. Unlike some years ago when there used to be quite a range of developing environments with software and hardware components of their own, this market now rather seems to focus on generating hardware-independent and synthesizable HDL. Graphic developing environments are increasing in scope so much so that the ‘developer’ need not be a software or hardware specialist at all. The result of this trend is that companies wanting to use an FPGA as an embedded system are likely to overcome their initial hesitation. Despite this positive evolution we have noticed, throughout our research, some less favourable tendencies on behalf of the developer. Mutual exchangeability between developing environments of different manufacturers is not quite unproblematic. New software versions and service packs succeed one another as quickly as lightning. The usage of FPGA as an Embedded system and the graphic developing environment presented for that purpose enable the software and hardware developers to market a reliable product within a short lapse of time.