Webinar Gravado: Um Estudo sobre a I2C e o Futuro com a I3C

May 2023
The Evolution of the Most
Widely used Serial Bus
A study of I2C, its applications, and future
with I3C

Agenda
1 Overview of I2C Protocol
2
I2C Open-Drain Bidirectional
Communication Basics and
Examples
3 Design and Application practices
4 Challenges associated with I2C
and Product Solutions
05 I2C NPIs
06 Why I3C?
07 Differences to I3C Standard
08 I3C Protocol

I2C
01 Overview of I2C Protocol
02 I2C Open-Drain Bidirectional
Communication Basics and Examples
03 Design and Application Practices
04 Challenges associated with I2C and
Product Solutions
05 I2C NPIs

Nexperia •
Overview of I2C Protocol: Development and History
nexperia.com - public 5
Why was I2C developed?
• The Inter-Integrated Circuit (I2C) was developed in 1982 by Phillips Semiconductor
• Primary aim to reduce complexity of communication between MCUs and peripherals
• Reduces wire count for communication, as opposed to SPI(Multiwire 1979)
• Two-wire multi-controller/target low speed serial bus (Standard mode 100kHz)
• Ease of implementation, 7-bit addressing allows 128 unique addresses (112 target devices/16 addresses reserved). 10-bit
extension available on some devices
• Multiple controllers and targets can be connected to same I2C Bus.
• Bi-directional data transfer to and from all devices.
• Two wires of I2C Bus are called SCL and SDA.
• SCL used to provide clock signal to synchronize data transfer
• SDA used to communicate address, data, and ack/nack
• Pins of I2C compliant devices are open-drain and need external pullup resistors

Nexperia •
Overview of I2C Protocol: Different Modes
6
Primary differences between I2C modes?
• Different Maximum Speeds.
• Different Maximum Capacitance values
I2C modes
Mode Maximum Capacitance Maximum Speed
Standard mode 400pF 100kHz
Fast mode 400pF 400kHz
Fast mode plus (Fm+) 550pF 1MHz
High-speed mode (Hs) 400pF 3.4MHz
https://assets.nexperia.com/documents/user-manual/UM10204.pdf
nexperia.com - public

Nexperia •
Overview of I2C Protocol: System Example

I2C Open-Drain Bidirectional
Communication Basics and
Examples
02

Nexperia •
I2C Open-Drain Bidirectional Communication Basics
• Buffer input
• MOSFET Open-Drain
configuration

Nexperia •
I2C Open-Drain Bidirectional Communication Basics
Start Condition: The controller pulls the SDA
line low while SCL is high, signaling the start of
communication.
Address Frame: The 7-bit (or possibly 10 bit)
sequence that is unique to each target device.
Read/Write Bit: The 8th bit follows the address
frame to signal to the target device whether
the controller is requesting or writing data.
ACK/NACK Bit: Every 8-bit frame in a message
is followed by an ACK/NACK. The target device
pulls down SDA signal to inform the controller
that the data frame was successfullyreceived.
Stop Condition: The controller releases the
SDA line from low to high, while SCL is high SCL Controller
MOSFET: Pulsing SCL
SDA Controller:
MOSFET: Communicating Address
frame.
Buffer: listening for “target” ACK
SCL Target:
Buffer: Receiving Data
MOSFET: Sending ACK
SCL
SDA

Nexperia •
I2C Operation Examples: Important specifications
SYMBOL PARAMETER TYPICAL UNITS
fSCL SCL clock frequency kHz
tLOW Low period of SCL signal us
tHIGH Higher period of SCL signal us
tr Rise time (SDA) ns
tf Fall time (SDA) ns
tSU(STA) Set-up time for Repeated Start us
tHD(STA) Hold time for Start/ Repeated Start us
tSU(DAT) Data set-up time ns
tHD(DAT) Data hold time us
tSU(STOP) Set-up time for stop condition us

Nexperia •
I2C Operation Examples: Timing parameters
Re-Start Setup Time and Re-Start/StartHold Time
Rise and Fall time
Data Setup time Stop Setup Time

Nexperia •
I2C Operation Examples: I2C User Manual
13
https://assets.nexperia.com/documents/user-manual/UM10204.pdf

Nexperia •
I2C Operation Examples: 8-bit Write
I2C: Target Device Register Write I2C: Target Device Register Read

Design and Application
Practices
03

Nexperia •
I2C Design and Application practices: Pull-up resistor
16

Nexperia •
I2C Design and Application practices: Pull-up resistor sizing Rp(max)
17
I2C
SDA
INPUT
I2C
SDA
OUTPUT
VDD SUPPLY
SDA pin
Rp
VO
MOSFET
Current
Cb
𝑉(𝑡) = 𝑉𝐷𝐷(1 − 𝑒−
𝑡
𝑅𝐶)
𝑉(𝑡1) = 0.3 × 𝑉𝐷𝐷 = 𝑉𝐷𝐷(1 − 𝑒−
𝑡1
𝑅𝐶) 𝑡ℎ𝑒𝑛 𝑡1 = 0.35667 × 𝑅𝐶
𝑉(𝑡2) = 0.7 × 𝑉𝐷𝐷 = 𝑉𝐷𝐷(1 − 𝑒
−
𝑡2
𝑅𝐶) 𝑡ℎ𝑒𝑛 𝑡2 = 1.20397 × 𝑅𝐶
tr=t2-t1=0.8473 × 𝑅𝐶
Rearranging equation:
𝑅𝑝(𝑚𝑎𝑥) =
𝑡𝑟
0.8473 × 𝐶𝑏

Nexperia •
I2C Design and Application practices: Pull-up resistor sizing Rp(min)
18
(VDD-VOLmax)/Rpmin= IOL
Rearranging equation:
Rpmin= (VDD-VOLmax)/IOL
I2C
SDA
INPUT
I2C
SDA
OUTPUT
VDD SUPPLY
SDA pin
Rp
VOL
MOSFET
Current

Nexperia •
I2C Design and Application practices: BUS net capacitance
19
TRACE WIDTH
TRACE THICKNESS
LAYER HEIGHT
εr
Imperial version:
CL = capacitance per unit length in pf/inch
w= width of the trace in mils
h = height of the trace above power plane in mils
t = thickness of trace in mils
εr = dielectric constant of material between
trace and power plane (FR-4 is ~4.5)
Metric version:
CL = capacitance per unit length in pf/cm
w= width of the trace in mm
h = height of the trace above power plane in mm
t = thickness of trace in mm
εr = dielectric constant of material between
trace and power plane (FR-4 is ~4.5)
LAYER
THICKNESS
C= εrεo(L*W)/d [F]
W
L
C = Parallel plate capacitance [F]
W= width of trace
L = Length of trace
d = thickness of dielectric
εr = (relative permattivity) dielectric constant of
material between trace and power plane (FR-4 is
~4.5)
εo = permittivity of a vacuum in Farads per
metre 8.85x10-14 [F/cm]
εr

Nexperia •
I2C Design and Application practices Layout strategies
20
SCL
SCL
SCL
SCL
SDA
SDA
SDA
SDA
External noise
Inductive noise
Better shielding

Challenges associated with
I2C and Product Solutions
04

Nexperia •
Challenges associated with I2C
22
>400pF
VOC Sensor
GPIO
Expander
Temp
Sensor
ADC
LED
Controller
Humidity
Sensor
DAC
I2C LCD
Display
PMIC
uC Controller
Rp
VDD
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
Controller Target Devices
EEPROM Digital Pot
Pressure
Sensor
Memory
Proximity
Sensor
Barometric
Sensor
3-axis acc Thermal Etc.
SDA
SCL
SDA
SCL
SDA

Nexperia •
Challenges associated with I2C: Device solutions
23
• Examples: Driving off-board communication
• Large cable capacitance
• Examples: Partitioning board devices
• 400pF each PORTX

Nexperia •
Challenges associated with I2C: Device Solutions
24
• GPIO expander to dynamically address
the target devices.
• Sets all address pins high, and when the
controller wants to communicate to a
specific device, it would set the device
address pin to low through the GPIO
expander
H
H
H
H
H
H
H
L

I2C NPIs
05

Nexperia •
1 In planning / considered
26
Public
I2C edge
repeater
Products
• NCA9700DQ
• NCA9701GX 1
Benefits
✓ Voltage level translation from
0.9V to 3.6V at both port A and
port B
✓ Guaranteed 1 MHz operation
(true I²C Fast-mode Plus, Fm+)
and can drive up to 550pF at
1MHz
✓ No static voltage offset, low VOL
✓ Input and output rising-edge
signal accelerators at all I/O’s
✓ Glitch-free and sequence-
independent IC power-up
Applications
• Cell phones / Tablets / PC
• Devices for IoT applications
• Power-sensitive applications
I2C NPIs
GPIO Expanders, Repeaters & Switches
I2C GPIO
Expander
Products
• NCA9555PW / NCA9555BY
• NCA9539PW
• NCA9535PW
• NCA9595PW
Benefits
✓ Operating voltage range
• VCC =0.9V – 3.6V
✓ 5V tolerant I/O’s (16)
✓ Power-up with all channels
configured as inputs with weak
pull-up resistors
✓ Glitch free power supply
sequencing
✓ Low Standby-Current
consumption
✓ Latched outputs with 25mA drive
Applications
• Servers, Routers
• Gaming consoles
I2C Switch
Products
• NCA9548PW (TSSOP24) 1
Benefits
✓ Operating voltage range
• VCC = 1.65V – 5.5V
✓ 1-to-8 Bidirectional translating
switches I2C Bus and SMBus
compatible
✓ Active-low reset input
✓ Glitch free power-up
✓ Low RON switches
✓ Channel selection through an I2C
Bus, in any combination
✓ Power up with all switch
channels deselected
Applications
• Products with I2C slave address
conflicts

Nexperia •
Product Introduction | NCA9555PW, NCA9555BY
27
Features
▪ Single supply GPIO expander supporting 1.65V to 5.5V operation
▪ Serial to parallel (SDA to P0-P16) and parallel to serial (P0-P16)
conversion with I2C protocol
▪ Schmitt-trigger action allows slow input transition and better switching
noise immunity at the SCL and SDA inputs
▪ Low power consumption 2.5 µA max
▪ 400 kHz operation (FM I2C mode)
▪ Glitch free Power up with all channels configured as inputs with Pull-ups
▪ Latched outputs with 25 mA drive maximum capability for directly
driving LEDs
▪ Polarity Inversion Register
▪ External RESET pin to reset state machine and internal registers
▪ Noise filters on SCL and SDA inputs
Benefits
❑ Reduces the PCB design complexity through trace reduction and
routing simplification
❑ Lowers I/O usage & reduces the system cost
❑ Board-space and Processor-pin saving
Functional block diagram
Applications
▪ Servers, Routers, Hardware control monitors, IOTs, Gaming consoles
▪ TV & Monitors, Battery powered applications and Automotive
Tools and Resources
▪ Datasheet NCA9555PW
▪ Evaluation Board (EVM), Demo Board
▪ Package Schematic Symbol
▪ Application note
▪ IBIS model
Public

Nexperia •
NCA95xx I²C GPIO expander – Application areas
28
VCC
NCA9555 #2
VCC
8
8
l
I²C
Control
Master
SDA SCL
NCA9555 #2
I²C Control
NCA9555 #1
I/O
Port 1
I/O
Port 1
INT
8
8
SCL SDA
Address
selection
LEDs
...
Switches
...
Enable 1
Vout 1
Vin 1
Enable N
Vout N
Vin N
From 16
to up to 128
I/O lines
IC controls & feedback signals
inputs (enable, mode select, ....)
outputs (power good, thermal
alarms, etc.)
SW 1 SW X
Generic readback of states
...
Public

Nexperia •
Features and Options
I2C GPIO Expander Family
29
NCA9555
NCA9539
NCA9535
NCA9595
16 Channel
NCA9539 NCA9555
NCA9535
NCA9595
RESET Pin
YES NO
Internal Pull-up
NCA9555
NO
NCA9535
NCA9539
YES
NO
NCA9595
YES
Configurable
Pull-ups
NCA9555, NCA9539 and NCA9535 are drop-in
replacement from competition TI and NXP
➢ TI: TCA9555, TCA9539, TCA9535
➢ NXP: PCA9555A, PCA9539A, PCA9535A
➢ NCA9555 will be available in TSSOP24 and
HWQFN24 package
➢ NCA9539 and NCA9535 will be available in
TSSOP24 package
NCA9595 is a new product in the market
featuring benefits such as low power
consumption and reduce BOM cost
➢ NCA9595 will be available in TSSOP24 and
HWQFN24 package (Sleeper)
Public

Nexperia •
NCA95xx I²C GPIO expander family – Types and their specifics
30
NCA95xx family
• NCA9555PW TSSOP24
NCA9555BY HWQFN24
- integrated 100 kΩ pull-up resistors for GPIO pins
- no integrated termination of GPIO pins
– advantage: no extra current for active outputs in low state
- additional 2 I²C registers for switchable pull-up resistors
- additional Reset pin (low active)
A2 address selection pin is sacrificed ( 4 adress options)
- no internal termination like NCA9435
Public

Nexperia •
Product Preview | NCA9701AGX/DQ
31
NCA9701AGX/DQ - Dual channel voltage translating I2C repeater / accelerator
• Server
• Routers
• Personal Computers
• Industrial Automation Equipment
• Products with many I2C slaves
and / or long PCB traces
 Dual channel bidirectional I2C buffer (Autosense topology)
 Voltage level translation from 0.9 V to 3.6 V at both port A and port B
 Guaranteed 1 MHz operation (true I²C Fast-mode Plus, Fm+)
 No static voltage offset, low VOL
 Very low VOL on I/O pins of the port A; VOL regulated to 0.09 * VCCB
on I/O pins of the port B
 Input and output rising-edge signal accelerators at all I/Os
 Lock-free operation
 Glitch-free and sequence-independent IC power-up
 Open-drain input/outputs
 Series connection and star connection of NCA9701A devices possible
 I²C clock stretching support
 Compatibility with I²C bus and SMBus protocols
 Integrated pull-up resistors (BOM cost reduction) and possibility of
connecting external pull-up resistors
 I2C clock stretching, and multiple master arbitration supported
Value proposition Key applications
Portfolio / release plan
Product CES [Wk] CQS [Wk] RFS [Wk]
NCA9700DQ Available May 2023 July 2023
Parametrics
Parametrics
Product VCCA, VCCB
Low-state
Current
Frequency
Data set-up time
gain
Temperature Range
NCA9700 0.9V – 3.6V
Both
channels
Low =
3.9mA
SM, FM, FM+
CL(A) = 10 pF; CL(B)
= 160pF  45ns
CL(A) = 85 pF; CL(B)
= 85 pF  104ns
−40 °C to 85 °C
Public
In Development, (Engineering Samples Available)

I3C
06 Why I3C
07 Differences to I2C Standard
08 I3C Protocol

Nexperia •
Why I3C?
Controller
Target
SCL
SDA
Target
INT
INT
Controller
Target
SCL
SDA
Target
Controller
Target
MISO
SCK
MOSI
Target
INT
INT
/CS0
/CS1
SLOW
Speed
Wiring
SPI I3C
I2C
34

Nexperia •
The I3C wiring advantage
I3C topology
MCU
(controller)
I3C
Temp
sensor
I3C
GPIO
I3C
ADC
I3C
Temp
sensor
I3C
DAC2
I3C
DAC1
I3C BUS
SDA&SCL
SDA
SCL
I3C target can take master
role
SDA&SCL
SDA&SCL
SDA&SCL
SDA&SCL
SDA&SCL
🚌
35

Nexperia •
The I3C Energy and Speed advantage
12,5
25
1
0
5
10
15
20
25
30
SDR DDR I2C FM+
RAW
Bitrate
[mBps]
Speed
0
0,5
1
1,5
2
2,5
3
3,5
4
SDR DDR I2C FM+
[mJoules
per
Megabit]
Energy
I3C I3C
Note: excluded higher speed / lower energy HDR-TSPL/TSP modes

Nexperia •
I3C Standardization

Differences to I2C Standard
07

Nexperia •
I3C physical level changes - SCL
SCL line is open drain
SCL line can be used bidirectional
(=> clock stretching feature)
I2C
SCL line is always operated in push pull mode
SCL line is unidirectional from controller to Target
I3C
I2C
Target
I2C
controller
R
Vcc
SCL
I3C
Target
I3C
controller
SCL
39

Nexperia •
I3C physical level changes - SDA
SDA is always open drain
SDA line is bidirectional
Additional usage:
acknowledge data transfer
I2C
SDA line is partially open drain and mostly operated in push pull mode
Additional usage:
Acknowledge in open drain mode
Push pull mode:
• Write transfer: DATA & Parity information
• Read transfer: DATA & Target can signal end of transfer
I3C
I2C
Target
I2C
controller
R
Vcc
SDA
I3C
Target
R
I3C
controller
SDA
I3C controller controls
Pull-up resistor or
high keeper
40

Nexperia •
I3C physical level changes – Push pull on SDA
When the bus is idle
After a start condition
During device address [*]
sending
For legacy I2C transfers
During Acknowledgment phases
Open drain active when:
Push-pull active when:
• In all other cases
• After a restart condition
push pull mode can be used
to send the target address
1 MHz [**]
[**] HS 3.4 MHz present,
but rarely used in real world
[*] A mixed push pull/open drain
addressing mode is also defined 41

Nexperia •
I3C modes
All modes work with max. 12.5 MHz clock
Speed [Mbit/s]
SDR 12.5
HDR-DDR 25
HDR-TS [*] ~37.5
Multi lane 100’s
[*] Ternary Symbol available in 2 flavors (pure and legacy)
=> SCL & SDA are used for data transfer 42

Nexperia •
Write transfers
I3C
I2C
Transfers
Note: Simplification - Many more transfer types are possible, e.g. with restart, longer data payload, …
ACK T-BIT
0x07
P
Address +
R/W bit
S
Controller
Target
ACK ACK
0x07
Address +
R/W bit
S
P
Read transfers
I3C
I2C
ACK T-BIT
DATA
P
Address +
R/W bit
S
ACK NAK
DATA
Address +
R/W bit
S
P
T-Bit for writes:
Controller sends a single
bit parity bit.
T-Bit for reads:
NOT a parity bit.
The target returns 1,
when it wants the
transfer to be finished.

Nexperia •
Write transfers
I3C
Transfers
ACK T-BIT
0x07
Address +
R/W bit
S
Controller
Target
P
Read transfers
I3C ACK T-BIT
DATA
Address +
R/W bit
S P
Open drain
low speed
PushPull
high speed

Nexperia •
I3C Disadvantages
Supports up to 50pF bus load only
Estimation are 10 .. 20 target devices (quote from MIPI alliance)
MIPI alliance is working on extending the range
A chance to invest into repeater circuits
Specified only from 1.2V onwards [*]
Already now it is clear that the lower side must be extended
IBI feature increases bus latency
Already now it is clear that the lower side must be extended
Specification quality & size
[*] for I3C basic spec

Nexperia • nexperia.com - public 47
[*] for I3C basic spec

Webinar Gravado: Um Estudo sobre a I2C e o Futuro com a I3C

Recomendados

Recomendados

Mais conteúdo relacionado

Semelhante a Webinar Gravado: Um Estudo sobre a I2C e o Futuro com a I3C

Semelhante a Webinar Gravado: Um Estudo sobre a I2C e o Futuro com a I3C (20)

Mais de Embarcados

Mais de Embarcados (20)

Webinar Gravado: Um Estudo sobre a I2C e o Futuro com a I3C