8. Cy-Net3 Module MICREL MICRF6x0 RF Transceiver eICE for direct debug eCOG1X14Z5 MCU Power Supply Jack RJ45 connector for Ethernet connection B-type USB Connector Memory Card Slot
This is an introduction to the CYAN CY-Net3 Network Module
Welcome to the training module on Cy-Net3 Network Module. This training module introduces Cy-Net3 network technology, and the USB/Ethernet Gateway module for Cy-Net3.
Mesh network topology is one of the key network architectures in which devices are connected with many redundant interconnections between network nodes such as routers. Messages sent on a mesh network can take several possible paths from source to destination. In many, but not al, mesh topologies routers provide an endpoint with a route to it’s destination that used the fewest number of retries over a time period when last checked. Endpoints can also request that a new check be made, which is called route discovery. In a mesh topology if any cable or node fails, there are many other ways for two nodes to communicate. While ease of troubleshooting and increased reliability are definite pluses, mesh networks are expensive to install because they use a lot of cabling.
Cy-Net3 offers a robust self-forming, self-healing mesh network capability for use with Cyan's eCOG range of microcontrollers. For wireless sensor networks, distributed control or low power networks, this provides an ideal solution. Cy-Net3 can be used with both low cost end nodes, and high capability gateway nodes. Cy-Net3 will run on RF hardware at any of the common frequency bands, such as 430MHz, 470MHz, 868MHz, 915MHz, and 2.4GHz. As Cy-Net3 uses mesh topology, it is capable for robust information delivery. Nodes may be added, removed or relocated without the need for explicit network reconfiguration. The network will dynamically reconfigure to respond to changes in the environment . The Cy-Net3 is designed for low power use, so it is ideally suited for long lifetime battery powered sensor nodes.
Some networks exist in isolation and it is usually necessary for control commands and data to be communicated remotely to the wireless network via a concentrator or gateway, interfacing to an entirely different protocol. The ubiquity of the internet and PC based systems means that this is usually Ethernet or alternatively USB. Because of their ubiquity, these protocols are often viewed as a commodity product but that does not make them any less complex. However, designers may not wish to invest the effort in understanding something that is not their core expertise and diverts them from their main tasks. Cy-Net3 can run on high capability Cyan gateway nodes, providing a bridge to Ethernet or USB connectivity.
Cy-Net3 can run as wireless sensor networks that require a large number of potentially low power sensors to report information back to a central gateway , such as home and building automation and security. It can also be used in industrial control applications where remote devices may need to be controlled from a central gateway, such as remote lighting control, asset tracking, and warehousing asset management. Another application is automated meter reading ( AMR ) and advanced metering infrastructure ( AMI ) which allow utility meters to be read and controlled from a central location, using a local gateway to communicate to a number of distributed nodes. In the first two cases, the entire network can be run using Cy-Net3 with the gateway node or nodes allowing a physical connection to a monitoring workstation. For AMR and AMI applications, a Cyan based gateway will perform a bridge to a wide area network back to base.
Cyan USB/Ethernet gateway for Cy-Net3 provides back channel connectivity, linking the RF network to a monitoring and control centre via the internet but also with USB peripheral capability and a memory card connector. It is a board level solution, including power socket and a connector for the debug interface. The Cy-Net3 protocol is handled by a Cyan eCoG1X microcontroller and use the Micrel Radiowire RF transceiver, operating in the unlicensed ISM bands at 433, 868 or 915MHz depending on geographic region. The main processor board includes a Cyan eCOG1X14Z5 microcontroller with on-chip Ethernet and USB peripherals.
Cy-Net3 is a flexible and lightweight fully mesh networking solution developed by Cyan, intrinsically supporting self forming and self healing functionality. The structure requires no master node. The Cy-Net3 stack running on Cyan eCOG microcontrollers offers a modular software environment based on the OSI standard networking model. It is supported by production ready node modules and gateways, and provides simple integration with a minimum of effort. It has a small memory footprint and is a reliable and robust, fully tested platform. The Cy-Net3 function is provided on the gateway by the inclusion of a Cyan module which includes an eCOG1X1A5 microcontroller, and a Micrel MICRF6xx Radiowire RF transceiver
Here is the simplified block diagram for Cy-Net3 Gateway board. The module use a Cyan eCOG1X14Z5 microcontroller as the processor. This device has a CPU core that operates at an internal clock frequency of up to 72 MHz, 512Kbytes of flash memory and 24Kbytes of SRAM. In addition to the memory within the eCOG1X MCU device, the module includes an additional 16 Mbytes of on-board SDRAM and a standard card socket for an SD or MMC memory card. The SDRAM is connected directly to the eCOG1X external memory interface bus. The eCOG1X14Z5 MCU includes a USB peripheral with an on-chip PHY, supporting low speed (1.5 Mb/s) and full speed (12 Mb/s) operation. The gateway board is available with a B-type USB connector. The eCOG1X14Z5 also includes an on-chip 10/100 Ethernet MAC. An external Micrel MICRF6x0 RF transceiver supports half duplex bi-direction RF links. With the Micrel radio transceiver, the system can perform FHSS operation with FSK modulation.
The eCOG1X14Z5 microcontroller is a low-power microcontroller, based on a 16-bit Harvard architecture with a 24-bit linear code address space (32Mbyte) and 16-bit linear data address space (128Kbytes). The CPU core is capable of operating at speeds 70MHz. Internal memory includes 512KB flash and 24KB SRAM for program and data storage. The Memory Management Unit (MMU) allows the combination of a variety of internal and external memories into a single logical memory structure. The External Memory Interface (EMI) allows connection of external memories to both code and data space of the CPU via the memory manager. Five clock sources are used to provide all internal system clocks. It also offers advanced peripheral functions including an on-chip USB controller and an Ethernet MAC. Software development is performed using the CyanIDE environment. It includes a full C compiler, source level debugger, Eclipse based IDE, and supports a direct debug connection to the target processor through a dedicated serial interface (eICE).
The RadioWire module product line is a familly of self-contained frequency shift keying (FSK) transceiver modules, intended for use in half-duplex, bidirectional RF links. These modules, designed to operate in the unlicensed ISM band, are the small, most cost-effective transceiver modules. These new modules are easy-to-operate, feature a small form factor and adhere to the European Telecommunication Standard Institute (ETSI) specification, EN300 220. The streamlined, “drop-in design” of the modules enables designers to quickly design new products by taking a more time-effective and cost conscious “cut and paste” approach to their RF reference designs.
The eCOG1X14Z5 MCU uses the CyanIDE environment, which includes an extensive USB support library for the eCOG1X. It includes a number of software “plugins” that can be added to applications to support common USB peripheral functions. It operates in USB host and peripheral modes, with support for On-The-Go functions. It supports low speed (1.5Mb/s), full speed (12Mb/s), and high speed (480Mb/s) modes. The USB core requires only 4Kbytes of working memory, used for the endpoint data buffers. This is taken from the top of the internal memory and cannot then be accessed directly by the processor. Reading and writing to this memory is always done either through the USB core FIFO registers or with the DMA peripheral and the slave FIFO.
The Ethernet MAC peripheral supports 10Mbits/s and 100Mbits/s operation with the appropriate external PHY device fitted. Both the transmit and receive data paths have their own separate 128 byte FIFO to provide data flow buffering. Data packets are stored in internal SRAM, accessed via the DMA controller. The software provided with the gateway includes source code and project templates based on the open-source uIP TCP/IP network stack. The uIP package provides an implementation of the TCP/IP protocol stack for embedded microcontrollers, without sacrificing interoperability or RFC standards compliance. It provides the necessary protocols for Internet communication, with very small code and data memory requirements.
Automated Meter Reading (AMR) refers to the technology used for automating collection of water and energy (electricity or gas) consumption data for the purposes of real-time billing and consumption analysis. At any given time, the AMR system gathers real-time data and transfers the information gathered to the central database through networking technology. This can be achieved using Cy-Net3 network. The figure shows the core features of a wireless meter reading application, collecting data values from remote meter units through the Cy-Net3 network and displaying the results via an http server to a LCD screen. The Cy-Net3 module can work as both remote meters and gateway.
Cy-Net3 is simple deployment, cost effective network solution. It has flexible architecture, which allows the network route efficiently from any point to any other point allowing applications to be client-server or peer-to-peer. Furthermore, efficient routing can prevent congestion as sometimes found in star/tree topologies. Data packets can find their way around broken nodes and links without manually configuring new routes. The dynamic routing enables data packets find the lowest cost route, not as the network was originally designed.
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