2)Sketch a schematic of the circuit described by the following HDL code. Simplify the schematic so that it shows a minimum number of gates. module exercise1(input a, b, c, d, output y, z); assign y = a & b & c | a & b & ~c & ~d | a & ~b & c & d; assign z = a & b | a & ~b | a & d; endmodule.