This document discusses methodologies and challenges for prototyping ASIC designs on FPGAs. Some key steps include making minor code modifications, identifying verification priorities, and good system partitioning. Challenges involve lowering system clocks, reducing design times, modifying clock trees to use FPGA resources, and carefully connecting and constraining interfaces between multiple FPGAs. Thorough report reviews are also important to check for timing issues, understand the clock tree, and ensure all pins are properly located and constrained.

1. ASIC PROTOYPING ON FPGA Zvi Goldenberg Engineer at Intel Senior Lecturer at Logtel May 4, 2011

2. Methodology and Challenges Very few code modifications Compromise readiness Identifying our customer ! (sw, design, be ) Define priorities – what is covered well by verification team ? Should I verify external IP’s ? Good system partition

3. Methodology and Challenges Lower system clocks (flow control may be used) Reduce design & synthesis cycle times (use compile point, FPGA editor etc.)

4. Clock tree modification

5. Simplifying clock tree Use FPGA PLL/MMCM by coregen Instantiate BUFG/BUFGCE/BUFGMUX Delete test mode clocking Use “fix gated clock” carefully Consider bypass clock gaters Refer to “gated clock” warning

6. System partitioning Try to locate FF at I/O pads (otherwise, in/out pad delay will reduce dramatically system performance) To save pin count: connect DDR/QDR/serdes between units (Adds latency , check if possible) Usually , phase of 2 FPGA’s must be equal Use PLL carefully to adjust Assign clk_FPGA_1_to_FPGA_2 = sys_clk_FPGA_1 won’t work – why ? Cont…

7. System partitioning Inter-connection pins : ddr/qdr/serdes may be added between units to save pins Tip : consider GTX serdes connection between 2 FPGA’s . This will enable system expansion. Tip : connect _gc pins from FPGA-1 to FPGA_2 to eliminate parasitic input delay on clock pins.

8. Reviewing reports Do I have slacks ? Are all pins located ? Are all pins got drive level + correct standard ? Did I constraint all clocks ? Answer: Run trce with –u Did I constrained all I/O’s offset ? - Same Do I understand all clock tree ? Search for derived clocks Cont…

9. Reviewing reports Do I have local clocks with large skew ? Did the tool understand my timing exceptions ? What is sampling window of main interfaces ? Answers can be found in .twr + .par + .csv reports Cont…

10. Reviewing reports I changed only version number and design stopped working !!! Possible reasons :

11. FPGA editor usage Invert input signal DCM /PLL Phase shift adjustment(manual calibration) Add pullup/down to pad Change drive level Change init value of FF/RAM Change logic equation of LUT add probes

12. Synthesis warning example case 0 case 1 … case 9 case 0 case 11.. case 19 Warning : case repetition

13. BUG example

14. TX RACE Inactive state must be ‘1’ (held by pull-up) when oen ↓ (close tx buffer) , input 1 of AND gate is driven to 0 >> data out_pad ==0 300 ps later buffer is closed >> data ↑ by pull-up (very slowly) Result : glitch detected by RX logic !!!!!!!! Found in Customer site 