Fostering Friendships - Enhancing Social Bonds in the Classroom
Nptel cad2-06 capcitances
1. CAD for VLSI Design - II
Lecture 6
V. Kamakoti and Shankar Balachandran
2. Overview of this Lecture
• CMOS Transistor Theory
– Delay Issues (Cont’d)
• Types and effects of Capacitances on delay
3. Parasitic Capacitance
• Switching speeds of MOS systems strongly depend on
the parasitic capacitances associated with MOSFETs
and interconnections
• Total Cload on the output of a CMOS gate is the sum of:
– Gate capacitance (Cg)
– Junction capacitance due to the source and drain
regions and their surroundings (Csb and Cdb)
– Interconnect (or routing) capacitance (Cw)
• Gate oxide capacitance per unit area,
ε ε
= 0 ox
ox
ox
C
t
5. Gate Capacitance
• Gate capacitance, Cg = Cox WL
• Total gate capacitance Cg can be
decomposed in two elements:
1. Overlap capacitance: due to the topological
structure of the MOSFET.
2. Gate-to-Channel capacitance: due to the
interaction between gate voltage and channel
charge.
6. Gate Overlap Capacitance
• In reality , actual channel length, Leff < drawn length, L
(mask length), due to the extension of the source and
drain regions somewhat below the oxide by an amount
xd, called the lateral diffusion, i.e., Leff = L – 2.xd
• xd gives rise to overlap capacitance which is linear and
has a fixed value.
Co is overlap capacitance per unit transistor width
(fF/μm)
= = =gso gdo ox d oC C C x W C W
8. Average Gate Capacitance
Region Cgb Cgs Cgd Cg
Cutoff CoxWL
eff
0 0
CoxWLeff/2
0
CoxWLeff+2CoW
Linear 0 CoxWLeff/2 CoxWLeff+2CoW
Saturation (2/3)CoxWLe
ff
(2/3)CoxWLeff+2C
oW
9. Area and Side-wall Capacitance
• Area Capacitance (Carea) due to the bottom-plate
junction formed by the source (drain) region with doping
ND and substrate with doping NA (bottom area 5).
• Side-wall (perimeter) Capacitance (Csw) formed by
junctions 2, 3, and 4. These are surrounded by the p+
channel-stop implant with doping level NA+ which is
usually larger than that of the substrate larger
capacitance per unit area.
= ,area j s jC C WL Cwhere is junction capacitanceperunitarea
( )
( )
where is junction side-wall capacitanceperunit
length
= + ⋅
′=
2
,
sw jsw s
j sw
jsw jsw j
C C W L
C
C C x
13. Modern Interconnect
• Inter-layer capacitance increases with decreasing feature
sizes.
• Multi-layer capacitive interactions result in unwanted
coupling among neighboring signals cross talk
16. 0.25μm Interconnect Hierarchy
• Optimize interconnect structure at
each layer.
– for local wires, density and low
C are important – use dense
and thin wiring grid
– for global wires in order to
reduce delays, use fat, widely
spaced wires.
• Improve wire delays by using
better material (Cu) and low-K
dielectrics for insulators.
Intracell
Intercell
Intermodule
Global
17. Electrical Wire Models
• Ideal Wire - it is simply a line with no attached
parameters or parasitics it has no impact on electrical
behavior.
• Lumped Model – simplified model simple and fast
computation, e.g., lumped C, lumped RC or lumped
RLC
• Distributed Model - Parasitics of a wire are distributed
along its length and are not lumped into a single
position, distributed C, distributed RC, or distributed
RLC
Clumped = lwire.cwire
18. Elmore Delay Formula
• For an n stage RC chain, the first order time constant is
given by,
• If Ri = Rj and Ci = Cj for all i and j , (1≤ i, j ≤ n) then,
( ) ( )
n i
n i j
i j
n nC R C R R C R
C R
R R
= =
τ
= + + + + + + +
= ∑ ∑
1 1 2 1 2 1 2
1 1
... ...
( )+
τ =
1
2
n
n n
RC
19. Distributed RC Model for a Wire
Using Elmore delay formula we can determine the dominant time constant
of the wire, i.e., it is a first-order approximation.
