Electronics Letters, IET, 6 Dec. 2012 Soo-Yong Kim, Keunhwi Koo and Sang Woo Kim

1. TIME-BASED POWER CONTROL
ARCHITECTURE FOR APPLICATION
PROCESSORS IN SMARTPHONES
Electronics Letters, IET, 6 Dec. 2012
Soo-Yong Kim, Keunhwi Koo and Sang Woo Kim
Advisor : Dr. Jenq-Shiou Leu
Student：Bing-Syuan Wang
Date：2014/11/28

2. Outline
• Introduction
• Time-based power control architecture
• Optimal power control
• Estimation of power consumption
• Conclusion

3. Introduction
• Application processors (APs) in recent smartphones are
integrated with multi-core CPUs and various intellectual
properties (IPs)
• Two modes for calling:
- Connected: transfer and receive data every 20 ms
- Idle: relevant communications standard
• Data patterns for memory read/write operations are
sparse and random

4. Introduction
• It is crucial but difficult to adopt conventional power-saving
techniques of power/clock gating and dynamic voltage
frequency scaling (DVFS)
• Conventional smartphones
- Power management system can easily gate the power
of the idle AP.
-The shared bus system is always enabled during simple
call modes.

5. Time-based power control architecture
• Clock/power gating is automatically performed without
intervention from the CPUs

6. Time-based power control architecture
• Transitions of power states according to data sequence
and circuit characteristics

7. Optimal power control
• The amount of power consumed by the overall system
• The performance index and the control input can be
represented as

8. Optimal power control
• To prevent performance degradation of the mobile
terminal, the processing times of the requests must satisfy
the conceded latency (Tlim).
• The moving average of the latency (Cl) is expressed as
• Since Lk is dependent on Tth and the types of the
requests, can be rewritten as

9. Optimal power control
• The latency is non-increasing and the power consumption
is convex with increasing Tth.

10. Estimation of power consumption
• Performed an electronic system level (ESL) simulation
with high-level models, traces of actual data traffic, a
power-saving algorithm, and power models

11. Estimation of power consumption
• Comparison of power consumption and latency

12. Conclusion
• This paper proposes a simple architecture to gate power
and clock into blocks.
• The simulation results show that the proposed
architecture exhibits low power consumption with
appropriate latency.