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IBM 3838Introduction: IBM 3838 is a multiple –pipeline scientific processor. It is evolved from theearlier IBM 2938 array processor. Both processors are specially designed to attach to IBMmainframes, like the System/370, for enhancing the vector-processing capability of the hostmachines. These attached pipeline processors reflect recent progress in scientific processing atIBM beyond the level of the 360/91 and 375/195. Vector instructions that can be executed inthe 3838 include the componentwise vector add, vector multiply, the inner product, the sum ofvector components, convolving multiply, vector move, vector factor conversion, fast Fouriertransforms, table interpolations, vector trigonometric and transcendental functions,polynomial evolution, and matrix operations. Like the AP-120B and the FPS-164, both the IBM2938 and the 3838 are the microprogrammed pipeline processor which can be supplied withcustom-ordered instruction sets for specific vector applications.Architecture: The hardware architecture of the IBM 3838 array processor is shown in thefigure 1. The processor can attach to a system/370 via block-multiplexer I/O channel with adata transfer rate of 1.5 byte per second. With an optional two type interface, the maximumdata transfer can be doubled to 3 byte per second. The 3838 appears to the host processor I/Ochannel as a shared control unit. Up to seven users can be simultaneously active in the 3838.The tasks by the each user is pipelined at the various pipelined at the various subsystem in the3838. The control processor can assist the user with the set of scalar instructions and thenecessary registers in preparing vector instruction. The bulk memory is used to hold largevolume vector operands. The I/O unit supervises the transfer of data or programs between thehost and the bulk memory. Data-word size of the 3838 is 32-bits, matching that of the system370. The transfer of the working sets of the vector segments between the bulk memory andthe working stores is supervised by the data transfer control (DTC). Each working store can hold8129 bytes. Vector-addressing parameters are supplied to the DTC by control processors. ThisDTC is microprogrammed to generate the effective memory addresses for both the bulk andworking memories before data can be properly transferred. Furthermore, the DTC can transferdata-format conversion during the data flow. The arithmetic controller is also amicroprogrammed unit. The microprogram sequences preformed by the arithmetic pipelinesare initialized by this controller. The use of working stores by the arithmetic pipelines and bythe DTC is synchronized. The basic pipeline cycle time is 100 ns in the 3838. There are five arithmetic units in the 3838. The pipeline units as diagram in the figure 1include two floating-point adders of four stages each; a four stage floating –point multiplier; athree stage sine/cosine pipeline; and a five-stage reciprocal estimator. Even the working storeappears as a four-stage pipeline. The delay of each stage is 100 ns. The interconnection pathsbetween these functional pipelines are under the microprogrammed control of the firstname.lastname@example.org M. TECH , CSE DEPARTMENT, NIT SILCHAR
element controller. The access of the writable control stage is also pipelined into two stagedelays. The programmed and the data to be processed by the 3838 are prepared by the hostcomputer. Both vector and scalar instructions can be contained in these 3838 programs. Thehosts send the program and the data to the 3838 through the I/O channel. Data will be storedin the bulk store. The instructions will be executed by the control processor. After decoding ofthe each instruction, the control processors provide link lists of microprogram sequences forsupervising the pipeline execution of the instructions. While the arithmetic pipelines areupdating vector data from one working store, the DTC can load the other working store. Thedata loading and the instruction execution can be done simultaneously at the two banks of theworking stores. This facilitates the multiprogrammed use of the 3838. Concurrent pipeliningallows multiple users to share the hardware resources in achieving high system throughput. Themaximum speed of the 3838 has been estimated to be 30 megaflops. Figure 1: The arithmetic Processor in IBM email@example.com M. TECH , CSE DEPARTMENT, NIT SILCHAR