1. VHDL 360© by: Amr Ali

2. Copyrights Copyright © 2010/2011 to authors. All rights reserved All content in this presentation, including charts, data, artwork and logos (from here on, "the Content"), is the property of Amr Ali or the corresponding owners, depending on the circumstances of publication, and is protected by national and international copyright laws. Authors are not personally liable for your usage of the Content that entailed casual or indirect destruction of anything or actions entailed to information profit loss or other losses. Users are granted to access, display, download and print portions of this presentation, solely for their own personal non-commercial use, provided that all proprietary notices are kept intact. Product names and trademarks mentioned in this presentation belong to their respective owners. VHDL 360 © 2

3. Objective Using Xilinx ISE* to Synthesize a given design unit Skills gained: Identify basic Synthesis flow VHDL 360 © 3 *All snapshots were taken using Xilinx version 11.4…They might vary based on the version you use. Please refer to www.xilinx.com for more info. Xilinx ISE is a registered trademark of Xilinx Corporation

4. Outline New Project Project Settings Import Files Synthesize View RTL Schematic Synthesis Report VHDL 360 © 4

5. New Project Open ISE File  "New Project" Specify project's name and location on disk VHDL 360 © 5

6. Project Settings Choose the target device press next  next  next  finish VHDL 360 © 6

7. Import Files to ISE RMB on the project node  Add copy of Source Browse the design files location on disk  select your files and press OK RMB on the design unit you want to synthesize and choose "Set as Top" VHDL 360 © 7

8. Synthesize Design Unit Select the design unit you want to synthesize double click on "Synthesize – XST" node VHDL 360 © 8

9. View RTL After synthesis finishes double click on "View RTL Schematic" node Choose "Start with a schematic" option and press OK VHDL 360 © 9

10. View RTL Double click on the top level diagram to see the RTL Explore the RTL netlist by hovering the mouse and double clicking on different blocks VHDL 360 © 10

11. Synthesis Report Switch to "Design Summary" tab and select the "Synthesis Report" node The Synthesis report is divided into sections including Area utilized by the design Estimate of the maximum operating frequency VHDL 360 © 11

12. Synthesis Report The "Synthesis Options Summary" section lists all the synthesis options used in this synthesis run To change synthesis options; RMB on the "Synthesis-XST" node  "Process Properties" VHDL 360 © 12

13. Contacts You can contact us at: http://www.embedded-tips.blogspot.com/ VHDL 360 © 13