paradigm Shift in VLSI

1. Introduction to Network-on-Chip
&
Low Power Routing algorithms
1
Presented by
Professor AJAL A J

2. Traditional SoC Issues
• Variety of dedicated interfaces
• Design and verification complexity
• Unpredictable performance
• Many underutilized wires
2
DMA CPU DSP
Bridge
IO IO IO
C
A
B Peripheral Bus
CPU Bus
Control
signals

3. NoC: A paradigm Shift in VLSI
3
s
s
s
s
s s
s
s
Module
Modul
e
s
Modul
e
From: Dedicated signal wires To: Shared network
Point-
To-point
Link
Network
switch
Computing
Module

4. 4
Processing
element
Network
Interface
Router
Input
buffers
directional
links
NOC- Working

5. 5
NOC- Working

6. Typical NoC Design Flow
6
Determine routing
and adjust link
capacities

7. Low Power Routing
algorithms

8. Network Topology
Direct In-direct

9. Direct Topology:

10. Topology:
10
PEPE PEPEPEPE PEPE
PEPE PEPEPEPE PEPE
PEPE PEPEPEPE PEPE
RR RR RR RR
RR RR RR RR
PEPE PEPEPEPE PEPE
RR RR RR RR
RR RR RR RR
The main problem with the mesh topology is its long diameter that has negative effect
on communication latency.
1. Mesh

11. Topology:
11
PE
PE
PE
PE PE
PE
PE
PE
SW
2.Octagon

12. Indirect Topology:

13. Topology:
13
SWSW
SWSW
SWSW
SWSWSWSW SWSWSWSW
PEPEPEPE PEPEPEPE PEPEPEPE PEPEPEPE
1.Tree

14. NoC Routing
Routing algorithm determine path(s) from
source to destination. Routing must prevent
deadlock, livelock , and starvation.
14

15. Deadlock, Livelock, and Starvation
Deadlock: A packet does not reach its destination,
because it is blocked at some intermediate
resource.
Livelock: A packet does not reach its destination,
because it enters a cyclic path.
Starvation: A packet does not reach its destination,
because some resource does not grant access (wile
it grants access to other packets).
15

16. Low Power Routing algorithms
1. XY Routing
2. Wormhole Routing

17. Routing examplesRouting examples
17
PEPE DDPEPE PEPE
PEPE PEPEPEPE PEPE
PEPE PEPEPEPE PEPE
RR RR RR RR
RR RR RR RR
PEPE PEPESS PEPE
RR RR RR RR
RR RR RR RR
Dimension Ordered Routing
(XY Routing)
X
Y

18. S
D
C o m m a n d
A d d r e s s
P a y lo a d
Wormhole Packet:
Flit
Flit
Flit
Wormhole Routing
For reduced buffering
Flit (routing info)
Flit
Flit

19. Wormhole Router
R o u te r
M o d u le
M o d u le
o r
a n o t h e r r o u t e r
CROSS-BAR
S c h e d u le r
C o n t r o l
R o u t i n g
C R E D IT
B u f fe r s
S IG N A L
R T
R D / W R
B L O C K
S IG N A L
R T
R D /W R
B L O C K
C R E D IT
S c h e d u le r
C o n t r o l
R o u t i n g
C R E D IT
S IG N A L
R T
R D / W R
B L O C K
S IG N A L
R T
R D /W R
B L O C K
C R E D IT
O u t p u t p o r t sI n p u t p o r t s

20. Status and Open Problems
• Power
– complex NI and switching/routing logic blocks are power hungry
– several times greater than for current bus-based approaches
• Latency
– additional delay to packetize/de-packetize data at NIs
– flow/congestion control and fault tolerance protocol overheads
– delays at the numerous switching stages encountered by packets
– even circuit switching has overhead (e.g. SOCBUS)
– lags behind what can be achieved with bus-based/dedicated wiring
• Lack of tools and benchmarks
• Simulation speed
– GHz clock frequencies, large network complexity, greater number
of PEs slow down simulation
20

21. Trends
• Move towards hybrid interconnection fabrics
– NoC-bus based
– Custom, heterogeneous topologies
• New interconnect paradigms
– Optical
– Wireless
– Carbon nanotube
21

22. THANK YOU!