2.5D, 3DIC and TSV Interconnect Patent Investigation Report 3DIC technology is seen today as a new paradigm for the future of the semiconductor industry: understanding the status of the patent situation is key to understanding the business situation. A very young patent landscape dominated by 10 companies... For this analysis of 3D packaging technology patents, more than 1800 patent families have been screened. 52% of the families have been classified as relevant and further studied. The indepth analysis quickly revealed that the overall patent landscape was pretty young with 82% of patents filed since 2006. Actually about 260 players are involved in 3DIC technology while the top 10 assignees represents 48% of patents filed in the 3DIC domain! We selected 5 companies from these 10 most active players to focus on and lead an accurate analysis of their patent portfolios. The report also provides a database of all the relevant patents we have analyzed in an Excel file which allows multi-criteria searching. The criteria are basically those we used for the technological segmentation: • Patent information ◦Patent publication number ◦ Link to the PDF document ◦ Oldest priority date ◦ Title ◦ Assignee ◦ Patent potential ranking ◦ Nb of citing patent families • Technological segmentation ◦Design ◦ Process: lithography, etching, metallization, passivation, filling, repassivation, UBM, bonding, thinning ◦ Test ◦ Architecture • End Application mentioned ◦Memory ◦ Interposer ◦ Logic Sip / SoC We found 4 main types of business models among the top 10 assignees involved in this mutating middleend area: • Foundries and IDM: IBM, Samsung, Intel • OSATs: STATS ChipPAC, Amkor • Memory IDM/Foundries: Micron, SK Hynix, Elpida • Research centers: ITRI It is also interesting to notice that the USA is the early player increasingly involved in 3DIC since 1969. China and Korea are new players since 2005. This complete description of the patent landscape is included in the first part of the report and provides all the background materials for the 3DIC patent landscape analysis. The report provides a complete analysis of the patent landscape including geographical origins of the patents, companies or R&D organizations that have been granted the patents, historical data on when the companies that have applied for patents in the last 20 years, inventors of the patents, expiration status, R&D collaborations… Understanding the patent portfolio of the top 10 3DIC asignees The report provides a deep dive into each of the patent portfolios of assignees selected by Yole Développement, including Intel, Samsung, Micron, IBM and TSMC. For each of these companies, the report provides an in-depth analysis of its patent portfolio, highlighting the following points: • Company patent portfolio evolution • Countries of deposition and origin of the patents • Top inventors

1. © 2013
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2.5D, 3DIC and TSV Interconnect
Patent Investigation Report
Infineon
MicronSynopsys
VTI
CEA LETI
Xilinx

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Table of Contents
• Why This Report?
• Companies Cited in the Report
• Introduction to 3DIC Technology
• Methodology for Patent Screening, Analysis and Ranking
• IP Landscape Overview
• Global Patent Ranking and Patent Potential Analysis
• Key Player Patent Portfolio Analysis
– Focus on Intel Corporation
– Focus on Samsung
– Focus on Micron
– Focus on IBM
– Focus on TSMC
• Conclusions and Perspectives
• Introduction & Presentation of Yole’s Activity
3
11
12
27
36
54
59
60
86
113
136
162
187
190

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Why This Report ?
• After several years of specific analysis for customers, YOLE Développement last
year started publishing reports on the analysis of the technical contents of
patents
• This new IP report is focused on the youngest advanced packaging technological
platform: 2.5D, 3DIC and TSV Interconnects
• YOLE has developed a specific methodology in order to make such analysis,
combining YOLE technical and business knowledge and classical access to
patent databases

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What This Report Does and Does Not Include ?
• It includes…
– This IP report provides an overview of « who is owning what » in terms of patents for the 3DIC
& 2.5D Interposer technologies, plus a dedicated focus on 5 players we consider as the most
active in this area
– The main report objectives are:
 To present the industrial and business status of the 3DIC today
 To define and provide a database of all the relevant patents with technological segmentation
 To detail architecture to be implemented
 To identify the key patents and the owners of such patents
• It does not include…
– Juridic analysis of patent portfolio
– Deep link analysis (legal, juridic…) between assignees
• To summarize, our work in the frame of the new kind of reports is to
analyze key patents to identify structuring concepts from a technological
or an industrial point of view, leading to business and strategic
conclusions

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Yole’s standard
reports
• Market analysis
• Technology analysis
A New Type of Report Providing a Clear Link
between IP Situation and Market Evolutions
• More than a report describing a state of the art of an IP situation, this report
provides a missing link between patented technological solutions and market,
technological and business trends
– YOLE has developed a unique methodology to define a technical segmentation of patent landscape,
as well as define which patents are the most innovative, either for future use or already in production
– By combining its technical knowledge, business understanding and patent search, this Yole report is
able to provide unique analysis and added value.
– In-depth technological analysis of patents provided in this report will lead to the understanding of
strategic decisions and positioning of key players within the value chain
3DIC Technological evolutions
& Market evolutions
3DIC IP landscape
Yole’s new IP report
• Relevant patents analysis
• Technological segmentation
• Detailed architecture to be implemented
• Key patent identification
• Links with the patents and available products

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Assumptions and Methodology (2/4)
Phase II depends on Phase I results.

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Companies Cited in This Report
A*STAR, Altera, AMD, Amkor, Apple, ASTRI, Avago, China
WLCSP, CISCO, Cypress, DNP, Elpida, Epson, GMEMS,
HITACHI, Hoya, IBM, IMEC, IMT MEMS, Infineon, Intel, IPDIA,
Irvine sensor, ITRI, JCET, KAIST, LG inotek, Lsi, Maxim,
Mediatek, Micron, Motorola, nVidia, NXP, OKI, Plan optik, PTI,
Qualcomm, Samsung, Sibdi, Silex, SK-Hynix, Sony,
StatsChipPAC, STMicroelectronics, Tecnisco, Teledyne Dalsa,
Tessera, Tezzaron, TI, tMt, Toshiba, TSMC, Visera, VTI Murata,
Xilinx, Xintec, and more !

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3D Integration: Halfway between SoC and SiP
“All-in-One chip system
integration Euphoria”
3DIC technology is seen
today as a new paradigm
for the future of the
semiconductor industry,
as it will enable several
more decades of chip
evolution at ever lower
cost, higher performance
and smaller-size
features.

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Why, When and How 3D?
The rapid evolution of 3D thinking in the IC community is astonishing
– Two years ago, the big question was “Why 3D?”
– Today’s questions are “When 3D?” and “How 3D?”
– In less than a decade from now, we will wonder “Why 2D?”
Evolution
or Revolution?
3DIC / 3D SoC
“De-integrated & Re-integrated SOC”
2D SOC
“All-in-One chip system integration”
All functions on 28nm lithography
 Chip area ↑, Cost ↑
MEMS 130 nm 200 mm
Memory 45 nm 300 mm
Logic 22 nm ? 450 mm ?
Analog 90 nm 300 mm
Thanks to 3D, heterogeneous
functions are integrated:
• On different lithography nodes
• On different wafer sizes
• In different wafer fabs
• By different players
 Cost ↓, Performance ↑, Size ↓

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Focus of the report !
Targeted Platforms for the IP Report
Advanced Packaging Platforms
RDL
BumpingBalling
Wafer Bonding
TSV
WL-
Optics
WL-
Capping
2.5D
Interposer
3DIC
Balling
WLCSP
FO
WLP
Embedded
IC
Flip
Chip
MEMS IC
Capping
IC
Sensor
Memory
Logic
3D
WLCSP
Die 1 Die 2 Die 3 Die 4
Middle-End Process Steps

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Definitions for Patent Analysis
• Patent family
– A patent family is a set of either patent applications or publications taken in multiple countries to protect a single invention by a common
inventor(s) and then patented in more than one country. A first application is made in one country – the priority – and is then extended to other
offices.
• Assignee (or applicant)
– An assignee is a person or organization (e.g. company, university, etc.) who/which has filed a patent application. There may be more than one
assignee per application. The assignee may also be the inventor.
• Priority date
– The priority date is the date on which the patent application was filed. At this date the patent document is not made available to the public.
• Priority Number
– The priority number is the number of the application with respect to which priority is claimed, i.e. it is the same as the application number of the
claimed priority document. The priority number is made up of a country code (two letters), the year of filing (four digits) and a serial number
(variable, maximum seven digits).
• Publication date
– The publication date is the date on which the patent application was first published. It is the date on which the patent document is made available
to the public, thereby becoming part of the state of the art.
• Publication number
– The publication number is the number assigned to a patent application on publication. Publication numbers are generally made up of a country
code (two letters) and a serial number (variable, one to twelve digits) (eg DE202004009768).
• International Patent Classification (IPC)
– The technical content of patent documents is classified in accordance with the International Patent Classification (IPC). The publishing office assigns
an IPC symbol valid at the time of publication of the patent application. The complete IPC can be found on the website of the World Intellectual
Property Organization (WIPO - http://www.wipo.int/ipcpub).

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IP Landscape Overview
 Distribution of All Analyzed Patents
 Overall Filing Trend
 Important Assignees

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Trend of Patent Filing for 3DIC Technologies
Patent Filing Trends for 3DIC Technologies
• 1013 patent families were filed from 1969 to 2012
• 82% of patents were filed since 2006
Yole Developpement © December 2012
0
20
40
60
80
100
120
140
160
180
200
220
240
260
1968 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012
No.ofPatentFamilies
Priority years

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Evolution of Top 15 Priority Countries for
3DIC Patents
• Bubble size represent number of published patent families. Note that World (WO) and
Europe (EP) codes may hide a significant portion of other countries patent activities
• USA is the early player increasingly involved in 3DIC since 1969. China and Korea are new
players since 2005
Evolution of Top 15 Priority Country for 3DIC Patents (related and relevant included)
Yole Developpement © December 2012

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Key Player Patent
Portfolio Analysis
 Company profiles
 Patent distribution and evolution
 Key patent family ranking, most cited patent identification
 Patent mapping
 Qualitative analysis of key patents

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Intel Patent Portfolio Analysis
• As an Integrated Device Manufacturer (IDM), Intel is involved in both
Design and Process development. However, almost 80% of the Intel’s
patents are dedicated to 3DIC & TSV process optimization
Design
8%
Process
79%
Architecture
13%
Intel Patent Portfolio Analysis
Breakdown by technological area
Yole Developpement © January 2013

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Intel Patents Describing TSV and 3DIC
Manufacturing Processes
• All the process steps for 3DIC manufacturing are described in Intel’s patents
– Bumping is the main area patented by Intel
– Followed by barrier/seed, TSV isolation, TSV etching and filling
 As an IDM, Intel is strongly focused on middle-end activities, epecially on
inter/intraconnections for 3D stacking
Lithography
4%
Etching
14%
Isolation
17%
Barrier / Seed
17%
Filling
14%
Bump / Passivation /
UBM /
21%
TB / TDB
10%
Thinning / Grinding
3%
Intel Patents Describing Process
Breakdown by process step
Yole Developpement © January 2013

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Assignee(s) INTEL (US)
Publication Number
(representative member)
US20060273455
No. of citing
patent families
48
Oldest priority date
of the family
2005-06-01 Legal status Alive: US20060273455
Title Electronic packaging including die with through silicon via
What is claimed:
- Die stacking through TSV, included in die, each active die separated with
silicon spacer
- Restrictive use of package leadless or not, QFP, SOIC, TSOP
- Definition of systems to use for this patent
Key words: TSV, Die to die stack, Package
Context: Reduced size of electronics package. Stacked die development.
Advantages / Prev.:
- Solder joint on TSV, to join 2 die, and also act as a spacer
- Shape of TSV with flexibility in the filling, not only metal, and can be filled
by dielectric in the middle of the TSV. Improvement can be from
mechanical point of view
- Flexibility of TSV design, through RDL done in the BEOL of die, to route
TSV not adjacent
Weakness:
- Cup shape of TSV can consume more area than vertical TSV
- Poor explanation on the description in the patent
Qualitative Analysis of Key Intel 3DIC Patents

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Assignee(s) INTEL (US)
Publication Number
(representative member)
US6229216
No. of citing
patent families
17
Oldest priority date
of the family
1999-01-11 Legal status
Alive: US6562653
Dead: US6229216
Title Silicon interposer and multi-chip-module (MCM) with through substrate vias
What is claimed:
- Die stacking package as shown in figure 3
- Electronic cartridge use the previous die stacking package, including heat
spreader
Key words: TSV, Interposer, Package
Context: IC package and thermal & mechanical aspects of package, with quality improvement.
Advantages / Prev.:
- Use of silicon interposer to connect plurality of IC, through solder bump
(silicon is matching CTE of IC, reducing the stress on solder bump)
- Interposer is built with TSV
- Use of small interposer, to act as a fan out, in order that the main
interposer is not limited with pad pitch
Weakness:
- Final package integration not easy to industrialize
- To bump top and bottom surface of interposer
- Poor claim
Qualitative Analysis of Key Intel 3DIC Patents

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Samsung Strategic Position in 3DIC Platforms
Global wafer forecast - breakdown by segment (12’’eq. wafers)
• Samsung already owns IP and has 3D devices in production in 3D WLCSP and 3DIC
platforms for CMOS image sensors (respectively FSI and BSI).
• It is also involved in the hybrid memory cube consortium with SK-Hynix, Micron and IBM.
This HMC is expected to be a key turning point in 2013 for 3DIC HVM manufacturing.
• Finally, Samsung has strong 3D SiP/SoC activity and is expected to ship the first 3D APE in
2015.
-
1 000 000
2 000 000
3 000 000
4 000 000
5 000 000
6 000 000
2 010 2 011 2 012 2 013 2 014 2 015 2 016 2 017
3D Stacked NAND Flash - - - - - 8 877 20 130 288 150
3D Wide IO Memory - - - - 110 215 252 005 896 565 1 429 417
Logic 3D SiP / SoC - - - 8 694 55 694 235 157 565 294 1 043 015
3D Stacked DRAM - 15 954 50 563 146 200 324 563 593 361 878 729 1 596 526
MEMS / Sensors 92 18 664 49 431 62 119 104 941 158 674 228 727 305 883
RF, Power, Analog & Mixed signal 10 723 16 027 23 006 39 654 61 102 84 445 110 921 146 403
Imaging & Optoelectronics 42 578 85 874 132 977 174 210 244 701 338 943 449 618 603 606
Wafercount(12''eqwafers)
3DIC Platform Wafer Forecast
Breakdown by Segment (12''eq wafers)
Yole Developpement © July 2012
TOTAL 53 394 136 519 255 977 430 877 791 001 1 419 457 2 253 420 5 413 001

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About the Author of This Report
Lionel Cadix
– Lionel joined Yole after completing several projects linked to the
characterization and modeling of high-density TSV and 3DIC chip stacking in
collaboration with CEA-Leti and STMicroelectronics for his PhD. He is the
author of several publications and holds eight patents in the field of 3D
Integration
Contact: cadix@yole.fr

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MEMS Packaging
Market & Technology Trends
1995
Sidebraze DIP
1996-20
02
Plastic
PDIP
1999 - today
SM
T SO
IC
& Die Down
2006
Stacked Die
QFN
~125 sq
mm
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mm ~25 sq
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6 & 6 mm
1995
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1996-20
02
Plastic
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1999 - today
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T SO
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& Die Down
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QFN
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mm
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mm ~25 sq
mm
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