Java Memory Consistency Model is a difficult topic. It's useful in making sure that multi-threaded programs on multi-threaded cores will interact with each other (and through memory) in a consistent manner. It's specification is damn hard (even according to folks with lots of concurrent experience, like Doug Lea) to read, understand and routinely follow without error. This presentation talks about some fallacies surrounding memory model, explains it, offers definitions and reasons for it's existence. It ain't deep, it's more entry level stuff.

1. Java Memory Consistency Model
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Tomasz Borek

2. GeeCON 2015 Kraków!
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http://2015.geecon.org/register/

3. I'll take ALL feedback I can get.
@LAFK_pl, #JMCM
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4. Symentis
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5. Symentis
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Jarosław Pałka Kuba Marchwicki

6. Today...
● A little bragging
● Fallacy correction
● Memory model
● The Java one mostly
● Short advice what about it
● Lot of links for later reading
● Yeah, 45 minutes only :P
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7. Who knows (heard of)?
● Gene Amdahl?
● Gordon Moore?
● Leslie Lamporte?
● Bill Pugh?
● Sarita Adve?
● Hans Boehm?
● Martin Thompson?
● Aleksey Shipilev?
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8. Hands up, who...
● Doesn't program
● Knows Moore's law?
● Knows Amdahl's law?
● Can explain concurrency vs parallelism?
● Codes with mechanical sympathy?
● Tries to?
● Knows what mechanical sympathy is?
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9. Fallacy #0
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Java Memory Model is about GC, memory
management, Eden, Survivors etc.

10. Not true at all!
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Java Memory Model is about GC, memory
management, Eden, Survivors, etc.

11. @LAFK_pl

12. MANAGEMENT!!
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13. Written in 2012...
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14. … and still there
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15. Correction!
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16. JLS, section 17.4:
A memory model describes, given a program and
an execution trace of that program, whether the
execution trace is a legal execution of the
program. The Java programming language
memory model works by examining each read in
an execution trace and checking that the write
observed by that read is valid according to certain
rules.
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17. JLS, section 17.4:
A memory model describes, given a program and
an execution trace of that program, whether the
execution trace is a legal execution of the
program. The Java programming language
memory model works by examining each read in
an execution trace and checking that the write
observed by that read is valid according to
certain rules.
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18. Sarita Adve: memory consistency
model
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19. Aleksey Shipilev:
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Memory model answers one simple question:
What values can a particular read in a program
return?

20. Bill Pugh, Jeremy Manson
● Most cores have many cache layers
● What if 2 cores look at same value?
● Memory model defines when and who sees
what
● There're strong and weak models
● Strong guarantee seeing same things across whole
system
● Weak only sometimes, via barriers / fences
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21. Bill Pugh, Jeremy Manson:
What is a memory model, anyway?
At the processor level, a memory model defines
necessary and sufficient conditions for knowing
that writes to memory by other processors are
visible to the current processor, and writes by the
current processor are visible to other processors.
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22. So?
● Memory CONSISTENCY
● Allowed optimisations
● Possible executions of a (possibly
multithreaded!) program
● Which cores / threads see which values
● How to make it consistent for programmers
● What you're allowed to assume
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23. Fallacy #1
I don't need to worry about JMCM since
REALLY smart engineers crafted it.
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24. Half-true
I don't need to worry about JMCM since
REALLY smart engineers crafted it
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25. Smart, sure! But still:
● Smart people are still people
● JMCM is damn hard! Yeah, they botched it.
● Java <> JVM
● JMCM is for JVM... but with Java in mind
● NO tech is a talisman of functionality!
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26. JSR-133?
● Messed up final
● Spec not for humans
● Messed up double-locking
● Messed up volatile
● Each implementation on it's own
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27. More?
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JEPS-188 and JMM9?

28. Fallacy #2
JMCM is irrelevant for me.
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29. Depends!
● What you write and with what
● Java? Not?
● Need performance?
● What platforms?
● Multicore era...
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30. Fallacy #3
JMCM is for fanatics. I have frameworks for that.
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31. Moore's ”law”?
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32. Moore's ”law”
I see Moore’s law dying here in the next decade
or so.
– Gordon Moore, 2015
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33. Amdahl's law?
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34. Amdahl's law
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The speedup of a program using multiple
processors in parallel computing is limited by the
sequential fraction of the program. For example, if
95% of the program can be parallelized, the
theoretical maximum speedup using parallel
computing would be 20× as shown in the
diagram, no matter how many processors are
used.
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35. Rok 1967, Gene Amdahl states:
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For over a decade prophets have voiced the
contention that the organization of a single
computer has reached its limits and that truly
significant advances can be made only by
interconnection of a multiplicity of computers in
such a manner as to permit cooperative solution.
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36. Rok 1967, Gene Amdahl states:
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For over a decade prophets have voiced the
contention that the organization of a single
computer has reached its limits and that truly
significant advances can be made only by
interconnection of a multiplicity of computers
in such a manner as to permit cooperative
solution.
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37. Cores... MOAR!!
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38. Data distance
● http://i.imgur.com/k0t1e.png

39. So, data distance varies
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Know thyne cache lines!
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40. @LAFK_pl
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So if it matters, what then?

41. Where it matters
● Javac / Jython / ...
● JIT
● Hardware, duh!
● Each time: another
team
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42. Hardware
● Various ISA CPUs
● Number of registers
● Caches size or type, buses implementations
● Cache protocols (MESI, AMD's MOESI, Intel's...)
● How many functional units per CPU
● How many CPUs
● Pipeline:
● Instruction decode > address decode > memory fetch
> register fetch > compute ...
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43. Program / code optimizations?
● Reorder
● (e.g. prescient store)
● Remove what's unnecessary
● (e.g. synchronize)
● Replace instructions / shorten machine code
● Function optimizations
● (e.g. Inlining)
● ...
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44. Exemplary CPU
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45. Barriers / fences
„once memory has been pushed to the cache
then a protocol of messages will occur to
ensure all caches are coherent for any shared
data. The techniques for making memory
visible from a processor core are known as
memory barriers or fences.
– Martin Thompson, Mechanical Sympathy
differs per architecture / CPU / cache type!
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46. Barriers / Fences
● CPU instruction
● Means ”flush BUFFER now!”
● CMPXCHG (may be
lacking!)
● Forces update
● Starts cache coherency
protocols
● Read / Write / Full
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47. @LAFK_pl
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Words of summary and gratitude

48. Doug Lea says:
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The best way is to build up a small repertoire of
constructions that you know the answers for and
then never think about the JMM rules again
unless you are forced to do so! Literally nobody
likes figuring things out of JMM rules as stated, or
can even routinely do so correctly. This is one of
the many reasons we need to overhaul JMM
someday.

49. Doug Lea advice:
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The best way is to build up a small repertoire
of constructions that you know the answers
for and then never think about the JMM rules
again unless you are forced to do so! Literally
nobody likes figuring things out of JMM rules as
stated, or can even routinely do so correctly. This
is one of the many reasons we need to overhaul
JMM someday.

50. Mechanical sympathy:
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● Cache lines misses hurt
● Going to main memory hurts
● Cycles are important
● L1, L2 caches are cheap but require cache
coherency protocols and memory barriers
● Not every hardware has all barriers
●

51. Gordon Moore
● Fairchild Semi-
conductors co-
founder
● ”Law author”
● Intel co-founder
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52. Gene Amdahl
● IBM fellow
● IBM & Amdahl
mainframes
● Coined law in 1967
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53. Leslie Lamport
● Distributed system
clocks
● Happens before
● Sequential
consistency
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54. Bill Pugh
● FindBugs
● Java Memory Model
is broken
● Final - Volatile
● Double-checked
locking
● ”New” JMM
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55. Sarita Adve
● Java Memory Model
is broken
● Great many MCM
papers
● Best MCM def I found
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56. Martin Thompson
● Mechanical sympathy
blog & mailing list
● Aeron protocol
● Mechanical sympathy
proponent
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57. This wouldn't have happened if not
● Jarek Pałka, who kicked me out here some
time ago
● Those folks, who said ”make more” after the
lightning talk I've done
● Java Day Kiev 2014
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58. Not possible without:
● Leslie Lamport's works on distributed sistems
● Bill Pugh's work on JSR-133!
http://www.cs.umd.edu/~pugh/java/memoryModel/jsr-133-faq.html
● Sarita Adve's paperts, especially shared MCM
tutorial:
http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf
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59. Terrific – and tough - reading
● Martin Thompson: Mechanical Sympathy (mailing list & blog)
● JEPS 188: http://openjdk.java.net/jeps/188
● Goetz et al: "Java Concurrency in Practice"
● Herilhy, Shavit, "The Art of Multiprocessor Programming"
● Adve, "Shared Memory Consistency Models: A Tutorial"
● Manson, "Special PoPL Issue: The Java Memory Model"
● Huisman, Petri, "JMM: A Formal Explanation"
● Aleksey Shipilev blog post: http://shipilev.net/blog/2014/jmm-pragmatics/
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60. Laws and related:
● Moore's ”law”:
http://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf
● Rock's law: http://en.wikipedia.org/wiki/Rock's_law
● Amdahl's law:
● http://en.wikipedia.org/wiki/Amdahl%27s_law
● Validity of the Single-Processor Approach to Achieving Large-Scale Computing
Capabilities AFIPS Press, 1967
●
J.L. Gustafson, “Reevaluating Amdahl’s Law,” Comm. ACM, May 1988
● Pleasantly parallel problems:
http://en.wikipedia.org/wiki/Embarrassingly_parallel
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61. Special thanks
● Konrad Malawski and Tomek Kowalczewski,
these guys really dig that stuff
● Bartosz Milewski who helped me rediscover
Hans Boehm
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62. YOU! You persevered through!
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