chapter 5.pptx: drainage and irrigation engineering
CNT embedded MOS DEVICES for Memory Application
1. Carbon nanotube embedded MOS structure for memory device
applications
A project work submitted for partial fulfillment of
M.Sc. (Instrumentation Science) degree
By
Soumit Bose
Roll no. MI1822002
2. INTRODUCTION
Research has been devoted to develop new materials and structures for several
applications in VLSI technology due to the increased use in portable electronic devices.
Applications such as solar cells, thin-film transistors, light emitting displays, radio
frequency identification (RFID) tags and sensors have been evaluated in the last few
years. Such devices attract electronic engineering, physics, and chemistry due to their
flexibility and low cost processing.
Non Volatile Memory (NVM) is becoming one of the emerging technologies in recent
days. Some of its applications are: (a) It is widely used in Mass Storage Memory such as,
NAND Memories, Hard Drives etc.; (b) It is used in Cache Memory for Enterprise
Storage; (c) It is used in Industrial Automation , Smart meter, Automotive; (d)They are
currently used widely in Embedded MCU for Smart Card such as SIM card, ID card.
One of the well-known memory structures is the floating gate-based memory device;
where typically a thin-film of a floating gate serves as a charge storage node in a
transistor or MIS structure. It is reported that a stable memory behaviour can be
achieved by charging nanoparticles or nanowires, which are integrated into the
insulating layer of the MIS structures or thin-film transistors.
3. Carbon nanotubes (CNTs) are hexagonally shaped arrangements of carbon atoms that have been rolled into
tubes.
• Diameter: less than 1 nm.
• Length: from a few nanometers up to a millimeter.
• Rolling up a graphene sheet may lead to a CNT (For imagination only!).
4. Properties of CNT
•CNTs have High Electrical Conductivity
•CNTs have Very High Tensile Strength
•CNTs are Highly Flexible- can be bent considerably without damage
•CNTs are Very Elastic ~18% elongation to failure
•CNTs have High Thermal Conductivity
•CNTs have a Low Thermal Expansion Coefficient
•CNTs are good reactives due to their Aspect Ratio
•CNTs have high Surface to Volume ratio.
5. WHY CNTs EMBEDDED IN FLOATING GATE?
A thin-film/discrete carbon nanotube (CNT) is one of the promising candidates for creating
the ubiquitous memory devices for the next generation of nanoelectronics. Due to the
high thermal stability, tuneable band gap, high aspect ratio, nearly zero surface states,
chemical inertness, as well as the excellent electrical properties and mechanical
strength, CNTs is well suited for memory applications where they may act as a charge
storage element in floating gate memory structures.
Now-a-days, high-ĸ dielectric materials are used as tunnel
and control oxides to improve the memory performance. In this report, an attempt has
been made to use the MWCNTs as charge storing sites where the MWCNTs are
sandwiched between HfO2 tunnel and control oxides to get a MOS structure.
6. AIM OF THE PROJECT
Characterization and discerning the acceptability of carbon nanotube to be used in MOS devices
for Non Volatile Memory device applications
7. What are NVM devices?
• Non-volatile memory (NVM) is a type of computer memory that has the capability
to hold saved data even if the power is turned off. Unlike volatile memory, NVM
does not require its memory data to be periodically refreshed. It is commonly used
for secondary storage or long-term consistent storage.
• Non-volatile memory is highly popular among digital media; it is widely used in
memory chips for USB memory sticks and digital cameras.
8. Different NVM devices
• The first type of devices is commonly known as “floating gate” (FG)
devices, where the charges are stored in polysilicon floating gates.
while the second type of devices is commonly known as “charge-
trapping” (CT) devices.
• The CT devices was earlier known as “discrete traps” or “embedded traps”.
• They could hold charges at the interface or bulk of a dielectric film with high
density of available “traps” or local “defects.”
9. Memory concepts in NVM devices
• Silicon based NVM device operates
like a metal–oxide–semiconductor
FET transistor.
• Electronic charges are stored within
the gate dielectric medium. The
process of storing the charges is
called the “writing” of the device. The
writing puts the device to an altered
high threshold state “Vth high” or
memory state “1.”
• The process of removing or
neutralizing the stored electronic
charge is called the “erasing” of the
device. The erasing puts the device to
a low threshold state “Vth low” or
memory state “0.”
10. CHARGE STORING PROCESS IN THIS MOS DEVICES
The two basic operation of the CNTs embedded MOS devices are:
1. PROGRAMMING OR WRITING IN THE CNTs
2. ERASING IN THE CNTs
11. PROGRAMMING OR WRITING IN THE CNTs
Programming is transferring of charge to the CNTs from substrate.
During writing process , a high gate voltage is applied at the gate voltage (say 10V),and the
source terminal is kept at ground, and a positive voltage is applied at the drain terminal(say
7V).The high gate voltage creates a inversion layer of electron between the source and drain
terminal. And as electrons move from source side to drain side some electrons are injected
through the tunnel oxide layer and get occupied in the CNTs .In these way CNTs can store
electron and thus Writing operation is established.
12. ERASING OF CHARGE OR DATA
Erasing means transferring charge from CNTs to Substrate.
During erasing process , the gate voltage is kept at ground terminal ,and the Source, Substrate and Drain are
raised to high voltage(say 10V) .The stored electron inside the CNTs are pushed away from the grounded Gate
terminal and are attracted towards the Substrate side. The tunneling oxide is kept very thin(~4nm),so the
electrons tunnels from CNTs and move towards the substrate side and thus cleaning the electron off the CNTs.
13. FABRICATION PROCEDURE
• The commercially available n-type silicon (100) wafers with a resistivity of 0.1-0.5 cm are
cut into several small pieces of area ~1 cm2 and used as Substrate of dimensions 1cm×1 cm.
• Then Si substrate are cleaned by RCA technique to remove the organic and metal
contaminates from silicon surface, respectively. The RCA (Radio Corporation of America)
clean is a standard set of wafer cleaning technique. Firstly, the Si substrates are cleaned
with RCA I (NH4OH: H2O2: deionized water (DI) = 1 : 1 : 5) solution at 75-80C is heated
for 10 minutes to remove the organic contaminates. Then the Si substrates are cleaned with
RCA II (HCl : H2O2 : deionized water = 1 : 1 : 5) solution at 75-80C for 10 minutes to
remove the metallic contaminates. The substrates were then dried.
• The cleaned Si substrates are then dipped in a 1% solution of Hydrofluoric acid (HF) + DI
H2O at 25oC for sixty seconds to remove the thin native oxide layer and some fraction of
ionic contaminants from the substrates. Finally, DI water rinsing and drying steps must be
performed properly. The HF etching is recommended to be performed just before the
loading into the deposition chamber since the Si surface are very reactive. After HF etching,
the samples were immediately loaded into the sputtering chamber.
14. • The HfO2 deposition was then carried out in argon plasma at a constant pressure of 6.6
x10−3
mB using 99.99% pure HfO2 target at 50W radio frequency power for 4 min. A 4nm-
thick HfO2tunneling oxide was deposited on the surface of the substrate.
• Commercially available MWCNTs, supplied by Sigma-Aldrich, were then coated onto the
tunnel oxide. The diameter of the CNTs was in the range between 110 – 170nm and the
length was in the range of 5 – 9µm. 2-Propanol was used as the solvent to prepare a stable
and homogeneous dispersion of purified (>90%) MWCNTs. In order to obtain a stable good
solution, the concentration of CNTs was fixed as 220mg/L. The solution along with
MWCNTs was ultrasonicated for 10 min. The homogeneous stable solution thus obtained
was filtered. MWCNTs were then drop-casted on HfO2/Si substrate to achieve its thin layer.
• The RF sputtering was again employed to deposit a 20 nm-thick HfO2film on
MWCNT/HfO2/Si substrates. The top HfO2 film acts as the control/barrier oxide.
• Aluminium was then evaporated on the sample using Electron beam evaporation system. The
Aluminium film was then patterned to electrodes of 100 µm diameter by Photolithography
technique to get the MOS structure.
17. RESULTS AND DISCUSSIONS
Two samples were taken for measurements
where one sample is without CNT
embedded MOS device and the other one
is CNT embedded MOS device.
The high frequency (HF) C-V
measurements were carried out on two sets
of MOS devices at 1 MHz frequency. The
HF C-V plots for the MOS devices are
shown in Fig. below. Data were taken for
CNT embedded MOS device where gate
voltage sweeps between -8 V↔+8 V. The
green line shows the writing cycles as
voltage is swept from +8 to -8 V. And the
blue line shows the erasing cycle as
voltage is swept from -8 to +8V.
The inset of the figure shows the HF C-V
characteristics of the MOS devices without
CNT where the gate voltage sweeps
between -5V↔+5V.
18. • The hysteresis loops in the C-V
curves indicate hole injection from
the substrate to CNTs under negative
voltage in the programming cycle
and electrons injection under positive
voltage during erasing cycle.
• The inset of the Fig. shows a
negligible hysteresis area for the
device without CNTs indicating no
charge storing property of the device.
• The area under the C-V curve
further indicates increasing charge
storing capacity with increasing gate
voltage for NVM MOS devices.
19. CONCLUSION
• The hysteresis loop area in the C-V characteristics of the CNT-
embedded MOS devices shows the charge holding capacity of the
CNTs when embedded in the HfO2 dielectric.
• Large memory window is also observed for the CNT-based
devices. The results indicate that the CNTs show a charge trapping
entity for non-volatile memory applications.
20. ADVANTAGES
1. CNT embedded devices show better performance in terms of charge storage
capabilities.
2. HfO2 is a better choice as the stacked tunneling oxide. High-k materials helps in
suppressing the leakage current. They have better charge retention then SiO2 gate
dielectrics.
3. Better Program / Erase cycles endurance.
4. CNT embedded Floating Gate MOS devices apply nanotechnology to improve device
performance.
Thus, CNT embedded MOS devices has the potential to replace
conventional Memory devices in the near future.
21. ACKNOWLEDGEMENT
It is my pleasure to express my gratitude to all those who have accompanied
and helped me in my project work.
First and foremost, I really take this opportunity to express my deep sense of
gratitude to my guide , DR. Supratic Chakraborty, of SINP,Kolkata-64,for his
invaluable guidance ,suggestions and encouragement throughout the project,
which helped me a lot to improve this project work. It has been very nice to be
under his guidance. His appreciation during the good times has been boosting
my morals and confidence.
Last, but not the least, I would like to thank my batch mates, seniors my
parents who have inspired me and helped me in this work.
