For the design of on‐chip ESD clamps against system level ESD stress three main challenges exist: reach a high failure current, ensure latch‐up immunity and limit transient overshoots. Bearing these in mind, high system level ESD requirements should be within reach. A novel improved high holding current SCR is introduced fulfilling all three requirements within drastically reduced silicon area. 

1. Conference paper On-Chip ESD Protection with Improved High
Holding Current SCR (HHISCR) Achieving IEC
8kV Contact System Level
EOS/ESD symposium 2010
For the design of on‐chip ESD clamps against system level ESD stress three
main challenges exist: reach a high failure current, ensure latch‐up
immunity and limit transient overshoots. Bearing these in mind, high
system level ESD requirements should be within reach. A novel improved
high holding current SCR is introduced fulfilling all three requirements
within drastically reduced silicon area.
Scan the code to get additional information.

2. On-Chip ESD Prot
Current SCR (HH
Sorgeloos Bart,
Sofics (formerly known a
phone: ++32-9-21-68
This
Abstract – For the design of on-chip E
reach a high failure current, ensure la
high system level ESD requirements
introduced fulfilling all three requireme
I. Introduction
System level ESD robustness is impo
the reliability for any product. Exte
ESD protection devices are widely
industry, but for some innovat
applications there is a trend induced
factor and operational performance to
board level devices and replace the
protection and thus connect I/O pins
harsh outside world. The on-chip ESD
up to increase its failure current which
issues with traditional ESD solutions
leakage, increased load capacitance
larger die area. Therefore, IC des
custom ESD protection structures wi
performance but within a small sili
maintaining the desired IC specificatio
Figure 1: Schematic representation of the co
with local protection between the Rx-input and
tection with Improved High
HISCR) Achieving IEC 8kV
System Level
Backers Ilse, Marichal Olivier, Keppens Ba
s Sarnoff Europe), Brugse Baan 188A, B-8470 Gistel, Be
8-333; fax: +32-9-3-746-846; e-mail: bsorgeloos@sofics.co
paper is co-copyrighted by Sofics and the ESD Association
Sofics BVBA BTW BE 0472.687.037 RPR Oostende
ESD clamps against system level ESD stress three m
atch-up immunity and limit transient overshoots. B
should be within reach. A novel improved high ho
ents within drastically reduced silicon area.
n
ortant to ensure
ernal (off-chip)
y used in the
tive consumer
d by cost, form
o remove these
em by on-chip
directly to the
clamp is scaled
h leads to many
s: increased pad
and especially
signers request
ith a high ESD
con area while
ons.
ommunication chip
VSS
This paper presents a case study
product where dedicated on-chi
protection is placed at the Rx
transmitter operates in an open dr
II. System Level ES
To fulfil system level ESD requ
ESD pulse shape and test setup
IEC 61000-4-2 standard [12], mar
1. High ESD current levels
30 ns (According to leve
2. A fast ESD current peak
rise time of 0.7ns-1ns.
3. The test must be d
operation under power
functional component in
Figure 2: The current waveform as defin
h Holding
V Contact
art
elgium,
om
main challenges exist:
earing these in mind,
olding current SCR is
y of a communication
ip system level ESD
x and Tx pins. The
rain configuration.
SD approach
uirements, the applied
must conform to the
rked by:
s: 16A current peak at
el 4 protection).
k value: 30A within a
done during normal
red condition of the
nside the system.
ned in the IEC standard
3A.1-1 EOS/ESD SYMPOSIUM 10-167

3. These standard system level test
translate into 3 basic rules that an a
level ESD clamp must comply to:
1. Achieve high ESD current leve
2. Limit voltage overshoot
3. No latched state after the ESD
A misconception is that all the ESD cu
directly through the IO. The system le
defined to perform the test on a syst
on the application this means that a p
current will flow through the shieldi
part will flow through the IO. Howe
part can still be a lot larger than the re
component ESD levels (HBM/MM).
One prevailing approach in testing for
applying the system level ESD pulse
IC, but this is not what the IEC 6100
[12] describes. For example, connectors
shell will only be stressed with conta
the metallic shell, while those with a p
only be stressed with air discharge.
Designing on-chip ESD devices wit
capability (16A) does not guarantee
level specification will be met. The
during system level ESD is to avoid a
soft failures in the system. These failu
by either EMI/EMC or due to IR drops
which could cause triggering of the P
Reset) circuit, change state of some reg
It is possible to conduct all the syste
through the on-chip ESD device, but a
is to provide the customer with an
protection featuring acceptable ESD v
with the necessary guidelines t
implement the chip on the board in th
guidelines ...).
The standard approach to protect these
based on the HHISCR (High holding
The next 3 sections provide the reas
device is an adequate protection for sys
1. SCR as a high current capable
Silicon Controlled Rectifiers (SCRs)
many ESD protection devices used i
They combine a lot of advantages
leakage/capacitance, low clamping
especially high current capability per
the SCR into an excellent device for hi
levels such as during system level ESD
specifications
adequate system
els
pulse
urrent will flow
evel standard is
tem. Depending
part of the ESD
ing and another
ever this second
equired standard
r IEC on chip is
e directly to the
00-4-2 standard
s with a metallic
act discharge on
plastic shell will
th high current
that the system
real challenge
any latch-up and
ures are induced
s inside the chip
POR (Power On
gisters ...
em level current
better approach
adequate ESD
values, and then
o successfully
he system (PCB
e applications is
g current SCR).
soning why this
stem level
le ESD device
are one of the
in the industry.
s such as low
voltage and
area. This turns
igh ESD current
D.
2. Reduction of overshoot
circuit
The overshoot of an SCR is main
trigger speed of the clamp (e
circuit)[13]. As will be shown fur
property can be kept below the
sensitive node. Especially for
overshoot should be limited for
to avoid any unrecoverable dam
prevent a disruption to the state
data).
3. Latch-up safe SCR solu
Current SCR
Aside from a high current carry
limited overshoot voltage, latch
third requirement for a sui
protection. To improve the latch
several techniques exist. One ap
voltage engineering technique (f
diodes) to attain a holding vol
supply voltage [1],[4],[5]. While th
up safe, the clamping voltage a
be higher, limiting its applicab
requirements. Another approach
high clamping voltage, is the
SCR (HHISCR) approach, pre
[1],[2],[9],[10] . The basic idea
trigger/holding current above t
spec (e.g. 200mA) / normal spe
through external shunt resistors
layout.
Figure 3: HHISCR as presented in [2]
The JEDEC latch-up test is on
latch-up story: the ESD protecti
trigger during this test. Howev
off-chip ESD protection, the on
turn on during the system leve
functional circuits. To prevent
condition changes so the device
system level pulse has passe
with a proper trigger
nly determined by the
especially the trigger
rther in the paper, this
failure voltage of the
system level ESD,
2 reasons. First of all
mage and secondly, to
e of the chip (loss of
ution: High Holding
ying capability and a
h-up immunity is the
itable system level
h-up safety of SCRs,
pproach is the holding
f.i. by adding holding
ltage larger than the
his approach is latch-
and on-resistance will
ility for high current
h, which solves this
high holding current
esented by Mergens
is to increase the
the JEDEC Latch-up
ecification (Figure 3)
s and a special SCR
nly one aspect of the
ion device should not
er, in the absence of
-chip protection must
el test to protect the
LU in that case, the
must turn off after the
ed. While the first
3A.1-2EOS/ESD SYMPOSIUM 10-168

4. condition generally relates to the trigger current of the
HHISCR, the second is mainly governed by its
holding current.
To determine the relevant holding current and voltage
of a stand-alone ESD clamp, an ESD stress pulse is
superposed on a DC bias level. When the DC bias
level is then stepwise decreased in subsequent
measurements, the exact holding voltage and current
can easily be established in the relevant time domain
(Figure 4).
Figure 4: Test set up to determine real holding voltage/current
For the system level ESD protection under normal
operation, the SCR must turn off after the ESD pulse
has disappeared. In this case the holding current of the
SCR must be above the maximum drive current of the
PMOS (15mA). Applying the above measurement
technique to the ESD clamp shows an effective
holding current above 22mA at a holding voltage of
2.45V. This proves that the SCR will turn off after
the system level ESD pulse is disappeared. The
holding current can be tuned further by the resistors
RSN and RSP and by the layout of the SCR body for
other applications.
Combining the high failure current and the
demonstrated latch-up immunity, the HHISCR is a
viable option for IO protection in this application. The
two remaining constraints are related to area
consumption and transient overshoot. The available
area was not sufficient to implement the standard
HHISCR, an improvement was needed to comply
with all specifications.
The next section presents an Improved HHISCR
device with an area reduction of 22% and a faster
SCR turn-on speed.
III. Integrated Trigger Approach
The standard HHISCR uses fully silicided poly
resistors or metal resistors (1-10 Ohm) and an NMOS
based trigger device. Instead of FS poly resistors,
active resistors (N+/PWell) can be used. Figure 5
shows the top view of the implemented diffusion
resistors. By applying a proper layout implementation,
a parasitic NPN bipolar transistor is formed between
the RSN (resistor between anode and G2) and RSP
(resistor between G1 and cathode). This NPN bipolar
acts as a trigger element replacing the NPN bipolar of
the NMOS trigger device. The bipolar is evenly
distributed across the resistors as shown in Figure 6
(b,c) for simplicity drawn as 3 separate devices. The
upper NPN bipolar is formed between anode and G1,
the lower NPN bipolar between G2 and GND and
another NPN bipolar is formed somewhere in
between. Note that each part of the NPN always sees
the same resistance (RSN, RSP or a combination of
these) given both resistors are of the same value.
Figure 5: Top view of the resistor implementation
The advantage of this distributed technique is that the
SCR is not triggered in only one of the two trigger
taps (G1, G2), but simultaneously in both trigger taps
improving the turn-on speed and reducing the
overshoot of the HHISCR. The basic device operation
is as follows (Figure 6/Figure 7):
1. Avalanching starts uniformly over the total
junction formed by the resistor RSN, but the
current at the anode will increase more
compared to the current at the G2 side of the
junction: the avalanche current flows through
the RSN resistor towards G2 which will induce
a voltage drop. The avalanche current will
turn on the NPNs between the 2 resistors but
the bipolar at the G2/cathode side will
conduct proportionally more current than the
other bipolars (difference in base-emitter
voltage due to resistive drops in RSP for each
bipolar).
P+ diffusion
N+ diffusion
Contact
Coupledto anodeCoupled toG2
Coupled tocathode
Coupledto G1
0 1 x-axis
RSNRSP
3A.1-3 EOS/ESD SYMPOSIUM 10-169

5. Figure 6: a) the standard HHISCR with only
bipolar) b) the NPN is formed distributed ove
trigger tap
2a. Conduction then spreads up
middle bipolar
2b. Finally, the current will be d
equally over the entire NPN.
3. When enough current flow
resistor, to build up a voltage
it, the base emitter of the NPN
forward biased, inducing
feedback and finally turning on
Figure 7: General IV curve of the Improved HH
the different regions 1, 2a, 2b and 3 related to
different parasitic elements inside the resistors
It is important to note that
elements/resistors must be separate
guard rings from the SCR and other ci
the formation of unwanted parasitic de
injection in G1 trigger tap (NMOS trigger device – also dep
r the 2 resistors (RSN, RSP) c) the NPN shown in b injects trig
pwards to the
distributed more
ws through the
of 0.7 V across
N or PNP will be
the positive
n the SCR.
HISCR highlighting
current flow in the
the trigger
ed with proper
ircuit to prevent
vices.
Simulations were performed to i
behaviour of the trigger d
distribution was simulated al
indicated in Figure 5). The RSN a
divided in different segments. F
NPN model was added and a m
avalanche current. The substrat
resistive network. (Figure 8)
Distributed
Susbtrate Mo
Cathode
RSNG2
RSP
Iav IQ,c
Figure 8: Simulation model
In Figure 9 the simulated aval
along the x-axis are plotted for
avalanche current is the hig
anode/substrate junction. All the
RSN resistor will contribute to th
but the anode/substrate region
icted by its intrinsic NPN
gger current in G1 and G2
investigate the current
device. The current
long the x-axis (as
and RSP resistors were
For each segment an
model to simulate the
e was modelled as a
d
odel
G1
Anode
Iav IQ,c
lanche current levels
r different times. The
ghest at position 1:
e junction area of the
he avalanche current,
will always see the
3A.1-4EOS/ESD SYMPOSIUM 10-170

6. highest voltage during the triggering and therefore
conduct the most current.
The avalanche current will pull the substrate voltage
above ground and the distributed bipolar will start to
conduct current.
Figure 9: Simulation of the current behaviour inside the trigger
device: avalanche current (Iav) at the RSN resistor
Figure 10 shows the bipolar current distribution along
the x-axis. First observation: the bipolar closest to the
G2-cathode side of the junction will conduct initially
the most current. This is because its base-emitter sees
the largest voltage drop. Second observation: the
bipolar closest to the anode junction will conduct
proportionally more current.
Figure 10: Simulation of the current behaviour inside the trigger
device: bipolar current (IQ,c) between RSN and RSP
IV. Analysis
1) Measurement results
Figure 11 compares TLP measurements of the
standard and the improved HHISCR devices (100ns
pulse width, 10ns rise time) showing a similar
clamping behaviour with a small difference in the
trigger voltage (Vt1). This is related to the different
type of trigger bipolar that is formed. The increase
from 8.5V to 8.8V stays within the design window for
this design. The most sensitive element is a NMOS
Gate oxide (gate source stress in inversion), with a
failure level of 13.5V (including safety margins) well
above the trigger voltage. Both devices remain within
the design window of the I/O pins. A slightly higher
failure current for the proposed device is observed due
to an increased failure voltage of the trigger bipolar
compared to the NMOS based trigger device.
Figure 11: TLP extracted IV curves
-04
-04
-03
-02
-02
-01
0 0.2 0.4 0.6 0.8 1
time 1
time 2
time 3
AvalancheCurrentditstribution
11
11
10
09
09
08
07
07
06
05
05
04
03
02
02
01
00
00
0 0.2 0.4 0.6 0.8 1
time 1
time 2
time 3
time 4
time 5
time 6
time 7
time 8
BipolarCurrentditstribution
0
1
2
3
4
5
6
7
0 2 4 6 8 10
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
HHISCR
Improved HHISCR
IDUT(A)
V DUT(V)
I
LEAKAGE
(A)
0
0.1
0.2
0.3
0.4
0.5
0.6
1 2 3 4 5 6 7 8 9
1 0
-8
10
-7
10
-6
10
-5
10
- 4
10
- 3
IDUT(A)
V DUT(V)
3A.1-5 EOS/ESD SYMPOSIUM 10-171

7. Figure 12 left: parallel implemented resistors; right: anti-parallel implemented resistors
2) Influence of the orientation of the resistors
This section investigates different resistor
configurations. In the implementation of figure 5, the
resistors were in a parallel orientation (Figure 12 left):
the anode connection of RSN adjacent to the G1
connection of RSP and the G2 connection close to the
cathode connection. A second possible
implementation is to place the resistors anti-parallel
(see Figure 12 right).
The difference between the two implementations is
that in the parallel implementation (Figure 12a) each
bipolar has RSN or RSP in series that will contribute to
build up 0.7V over the resistor and over the base
emitter junction of the bipolar transistors. In the anti-
parallel implementation (Figure 12b), the cathode is
adjacent to the anode instead of the G1 connection.
This has some implications: not all of the 3 indicated
bipolars will contribute equally to create the required
voltage build up to turn on the SCR. As seen in Figure
12b, the current flow through bipolar 1 will not
contribute to turn on the SCR (this current is flowing
direct from anode to cathode of the ESD clamp, so it
will not contribute to forward the base-emitter
junctions of the SCR).
The TLP results of the two implementations are
shown in Figure 13. The trigger current of the anti-
parallel implementation has increased from 273 mA to
469 mA without any constraint on the area or value of
the resistors.
Figure 13: Influence of the resistor orientation
Q3
12a2b
cathode
G1
G2
RSN
RSP
anode
Current flow
Current flow
RSN
RSP
Q1 Q2
anode
cathode G1
G2
Current flow
Current flow
RSN
RSP
anode
cathode G1
G2
2a2b 1
Parallel Implemented Resistors Anti-Parallel Implemented Resistors
cathode
G1
G2
RSN
RSP
anode
Q3Q1 Q2
topviewCurrentflow
Q1 Q2 Q3
Q1
Q2
Q3
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10
parallel implemented resistors
anti-parallel implemented resistors
I [A]
V [V]
Increase
of It1
3A.1-6EOS/ESD SYMPOSIUM 10-172

8. 3) Trigger voltage engineering
The trigger voltage of the clamp is
than the reference HHISCR (Figure 11
the fact that the trigger element is no lo
but an NPN formed between two N+ ju
Pwell. One technique to lower this tri
to add a gate between the resistors R
prevent the formation of oxide in
results in an improved and even fas
reduction of trigger voltage).
Figure 14: Improving the NPN by adding a
resistors
Figure 15:Trigger voltage engineering – TLP IV
0
0.05
0.1
0.15
0.2
4 5 6 7 8
Improved HHISCR
Improved MOS-HHISCR
HHISCR
I [A]
slightly higher
). This is due to
onger an NMOS
unctions and the
igger voltage is
Rsp and Rsn to
between. This
ster NPN (0.4V
a gate between the
V curves
4) Layout optimization
The previous implementations a
discrete resistors. The device cou
further by splitting the resistor
(Figure 16). The total width of
large enough to handle the tr
improved HHISCR to prevent d
circuit.
. . ,
With
1
,
,
The total length of trigger circuit
to handle the trigger current, re
design constraint.
. . ,
With
1
,
The third design parameter is the
which determines the trigger curr
.
.
With these 3 formulas the tri
designed.
5) Overshoot investigation
The improved HHISCR as propo
similar behaviour as the standa
pulses. By adding a gate betwe
trigger bipolar is improved (smal
on-resistance). This is character
analysis (Figure 17) by:
• An overshoot reduction
• A trigger speed enhancem9 10V [V]
always consisted of 2
uld be optimized even
s in different fingers
f the device must be
rigger current of the
damage of the trigger
, (1)
t must be long enough
esulting in the second
, (2)
e value of the resistor
rent
(3)
igger circuit can be
osed in Figure 6 has a
ard HHISCR for fast
een the resistors, the
ller base length, lower
rized in the transient
ment
3A.1-7 EOS/ESD SYMPOSIUM 10-173

9. Figure 16: Optimized layout of the trigger devic
Figure 17: Transient behaviour extracted with
system (2ns pulse width – 200 ps risetime)
V. Implementation
The optimal solution is the MOS-HHI
parallel resistors drawn according th
described in previous section. Th
successfully implemented both i
technology (3.3 V domain) and in a 0
technology (3.3 V domain).
The improved HHISCR has a simil
compared to the standard version but th
was decreased by 22%. This saving
integration of the trigger device in
layout of the resistors. (Figure 18)
The HBM level of the clamp exceed
of the tester in line with the expecta
Wb
Wa
RSN
Wa
RSN
RSP
Anode
Anode
G1
G2
G2
Cathode
ce
a standard vf-TLP
n
ISCR with anti-
he design rules
his clamp was
in a 0.13um
0.35 um CMOS
lar performance
he required area
g is due to the
the optimized
ds the 8kV limit
ations based on
SCR size. System level tests
product level, under powered co
any additional protection compon
pin passed 8kV contact and 15 k
chip protection against 8kV HBM
application since not all the curr
IO: a proper shield/ground im
discharges a part of the ESD cur
the configuration of the board
customer requirements will hav
needed on-chip ESD protection t
system-level ESD protection an
real world ESD protection.
Figure 18: Top view of the ESD layout
Wa Wa Wa Wa Wa
RSN
RSN
RSN
RSN
RSN
RSP
RSP
RSP
RSP
RSP
Anode
Anode
Anode
Anode
Anode
G1
G1
G1
G1
G1
G2
G2
G2
G2
G2
Cathode
Cathode
Cathode
Cathode
Cathode
StandardHHISCR
(IEC 61000-4-2) on
onditions and without
nents at the connector
kV air discharge. On-
M was enough for this
rent flows through the
mplementation already
rrent. The application,
d/connectors and the
ve an impact on the
to achieve the desired
d more important the
ImprovedHHISCR
3A.1-8EOS/ESD SYMPOSIUM 10-174

10. The high current ESD level is achieved while the
leakage is below 330 pA (VDD +10%) and 33 nA at
elevated temperature (125°C). (Figure 19)
Figure 19: Low leakage at room and elevated temperatures
Conclusion
High current levels, limited overshoot and latch-up
safety are the key aspects for a successful system level
implementation. This paper showed that optimized
layout of the HHISCR [11] can reduce the needed area
to reach system level ESD requirements by
integrating the trigger device into the resistor layout.
Acknowledgements
The authors would like to thank Natarajan M Iyer for
his valuable suggestions to improve the structure of
the paper.
References
[1] M. Mergens, “Advanced SCR ESD Protection
Circuits for CMOS / SOI Nanotechnologies”,
CICC 2005
[2] M. Mergens, “High Holding Current SCR
(HHI-SCR) for ESD Protection and Latch-up
Immune IC Operation.”, EOS/ESD 2002
[3] T. Smedes, “Relations between system level
ESD and (vf-)TLP”, EOS/ESD 2006
[4] M. Ker, “Overview of On-Chip Electrostatic
Discharge Protection Design With SCR-based
Devices in CMOS Integrated Circuits”, IEEE
Trans. Device and Materials Reliability, June
2005
[5] C. Russ , “GGSCRs: GGNMOS Triggered
Silicon Controlled Rectifiers for ESD
Protection in Deep Sub-Micron CMOS
Processes.”, EOS/ESD 2001
[6] M. Roseeuw, “On-Chip ESD Protection
Achieving 8kV HBM Without Compromising
the 3.4Gbps HDMI Interface”, RCJ 2009
[7] V.A. Vashchenko, ”System Level and Hot
Plug-in Protection of High Voltage Transient
Pins“, EOS/ESD 2009
[8] D. Robinson-Hahn, “Is System-Level ESD
Testing Valid for ICs?”, Power Electronics
Rechnoloby, september 2009
[9] US 6,803,633, “Electrostatic Discharge
Protection Structures Having High Holding
Current For Latch-Up Immunity”
[10] US 7,064,393, “Electrostatic Discharge
Protection Structures Having High Holding
Current For Latch-Up Immunity”
[11] US 2010/0008002, “High Trigger Current
Silicon Controlled Rectifier”
[12] IEC 61000-4-2, Edition 2.0
[13] G. Wybo. “Characterizing the Transient Device
Behavior of SCRs by means of VFTLP
Waveform Analysis”, EOS/ESD 2007
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
0 1 2 3 4 5 6 7 8 9 10
current(A)
Voltage (V)
25C
85C
125C
3A.1-9 EOS/ESD SYMPOSIUM 10-175

11. THIS PAGE WAS INTENTIONALLY LEFT BLANK
3A.1-10EOS/ESD SYMPOSIUM 10-176

12. Sofics Proprietary – ©2011
About Sofics
Sofics (www.sofics.com) is the world leader in on‐chip ESD protection. Its
patented technology is proven in more than a thousand IC designs across all
major foundries and process nodes. IC companies of all sizes rely on Sofics for off‐
the‐shelf or custom‐crafted solutions to protect overvoltage I/Os, other non‐
standard I/Os, and high‐voltage ICs, including those that require system‐level
protection on the chip. Sofics technology produces smaller I/Os than any generic
ESD configuration. It also permits twice the IC performance in high‐frequency and
high‐speed applications. Sofics ESD solutions and service begin where the foundry
design manual ends.
Our service and support
Our business models include
• Single‐use, multi‐use or royalty bearing license for ESD clamps
• Services to customize ESD protection
o Enable unique requirements for Latch‐up, ESD, EOS
o Layout, metallization and aspect ratio customization
o Area, capacitance, leakage optimization
• Transfer of individual clamps to another target technology
• Develop custom ESD clamps for foundry or proprietary process
• Debugging and correcting an existing IC or IO
• ESD testing and analysis
Notes
As is the case with many published ESD design solutions, the techniques and
protection solutions described in this data sheet are protected by patents and
patents pending and cannot be copied freely. PowerQubic, TakeCharge, and
Sofics are trademarks of Sofics BVBA.
Version
May 2011
ESD SOLUTIONS AT YOUR FINGERTIPS
Sofics BVBA
Groendreef 31
B‐9880 Aalter, Belgium
(tel) +32‐9‐21‐68‐333
(fax) +32‐9‐37‐46‐846
bd@sofics.com
RPR 0472.687.037