CSE 1205

1. Digital Logic & Design
Lecture 01
Rubya Afrin
Lecturer
Northern University of Business and Technology

2. Course Outline
CSE 1205: Digital Logic Design C. Hrs. 3.00
Digital logic, Boolean algebra, De Morgan’s Theorem, Boolean function, Canonical forms,
Minimization of Boolean functions, Logic gates and their truth tables, Canonical forms,
Minimization technique, Arithmetic and data handling logic circuits. Decoders, Encoders,
Multiplexer, De-multiplexer. Combinational Circuit Design, Electronic circuits for flip-flop,
counters, registers and memory devices. PLA design, Synchronous and asynchronous logic
design, state diagram, Mealy and Moore machine, state minimization and assignments, pulse
mode design, Fundamental mode design.
Recommended books:
1. Digital Logic & Computer Design : Morris Mano
2. Digital Systems: Principles and : Ronald J. Tocci, Neal S. Widmar,
3. Applications Gregory L. Moss

3. Grading
Attendance 5
Class test, Assignment, Presentation 25
Mid Term 30
Final Exam 40
Total 100

4. Analogue Quantities
Continuous Quantity
 Intensity of Light
 Temperature
 Velocity

5. Digital Values
 Discrete set of values

6. Continuous Signal
0
5
10
15
20
25
30
35
40
45
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
time
temperature0
C

7. Digital Representation
1 2
4
7
18
34
25
23
35
37
29
42 41
25
22
0
5
10
15
20
25
30
35
40
45
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
samples
temperature0
C

8. Digital Systems
 Two Voltage Levels
 Two States
 On/Off
 Black/White
 Hot/Cold
 Stationary/Moving

9. Binary Number System
 Binary Numbers
 Representing Multiple Values
 Combination of 0v & 5v

10. Logic Gates
 Building Blocks
 AND, OR and NOT Gates
 NAND, NOR, XOR and XNOR Gates
 Integrated Circuits (ICs)

11. Logic Gate Symbol and ICs
1
2
3
4
5
6
GND
Vcc
13
12
11
10
9
8
7400

12. Combinational Circuits
 Combination of Logic Gates
 Adder Combinational Circuit

13. Adder Combinational Circuit
Sum
Carry

14. Functional Devices
 Functional Devices
 Adders
 Comparators
 Encoders/Decoders
 Multiplexers/Demultiplexers

15. Sequential Circuits
 Memory Element
 Current & Previous State
 Flip-Flops
 Counters & Registers

16. Block Diagram of a Sequential Circuit

17. Programmable Logic Devices (PLDs)
 Configurable Hardware
 Combinational Circuits
 Sequential Circuits
 Low chip count
 Lower Cost
 Short development time

18. Memory
 Storage
 RAM (Random Access Memory)
 Read-Write
 Volatile
 ROM (Read-Only Memory)
 Read-Only
 Non-Volatile

19. Binary Number System
 Two unique numbers 0 and 1
 Base – 2
 A binary digit is a bit
 Combination of bits to represent
larger values

20. Binary Number System
Decimal Number Binary Number Decimal Number Binary Number
0 0 10 1010
1 1 11 1011
2 10 12 1100
3 11 13 1101
4 100 14 1110
5 101 15 1111
6 110 16 10000
7 111 17 10001
8 1000 18 10010
9 1001 19 10011

21. Combination of Binary Bits
 Combination of Bits
 100112 = 1910
= (1 x 24
) + (0 x 23
) + (0 x 22
) + (1 x 21
)
+ (1 x 20
)
= (1 x 16) + (0 x 8) + (0 x 4) + (1 x 2)
+ (1 x 1)
= 16 + 0 + 0 + 2 + 1
= 19

22. Fractions in Binary
 Fractions in Binary
 1011.1012 = 11.625
= (1 x 23
) + (0 x 22
) + (1 x 21
) + (1 x 20
)+ (1 x 2-1
) + (0 x 2-2
) + (1 x 2-3
)
= (1 x 8) + (0 x 4) + (1 x 2) + (1 x 1)+ (1 x 1/2) + (0 x 1/4) + (1 x 1/8)
= 8 + 0 + 2 + 1 + 0.5 + 0 + 0.125
= 11.625
 Floating Point Notations

23. Decimal-Binary Conversion
 Binary to Decimal Conversion
 Sum-of-Weights
 Adding weights of non-zero terms
 Decimal to Binary Conversion
 Sum-of-Weights (in reverse)
 Repeated Division by 2

24. Number Weight Result after subtraction Binary
392 256 392-256=136 1
136 128 136-128=8 1
8 54 0
8 32 0
8 16 0
8 8 8-8=0 1
0 4 0
0 2 0
0 1 0
Decimal to binary conversion using
Sum of weight

25. Decimal-Binary Conversion
 Binary to Decimal Conversion
 Sum-of-Weights
 Adding weights of non-zero terms
2
4 3 2 1
0
10011
(1 2 ) (0 2 ) (0 2 ) (1 2 )
(1 2 )
× + × + × + ×
+ ×
Terms 16,0,0.2 and 1
19

26. 2’s Complement form
 1’s complement form
 2’s complement form
Binary number 01101 (13)
1’s complement 10010
+ 1
2’s complement 10011 (-13)

27. Addition and Subtraction with 2’s
Complement
0101 +5 0101 +5
0010 +2 1110 -2
0111 +7 10011 +3
1011 -5 1011 -5
1110 -2 0010 +2
11001 -7 1101 -3

28. BCD (Binary Coded Decimal) Code
Decimal BCD Decimal BCD
0 0000 5 0101
1 0001 6 0110
2 0010 7 0111
3 0011 8 1000
4 0100 9 1001

29. BCD Addition
 Multi-digit BCD numbers can be added
together
23 0010 0011
45 0100 0101
68 0110 1000
23 0010 0011
48 0100 1000
71 0110 1011
 1011 is illegal BCD number

30. BCD Addition
 Add a 0110 (6) to an invalid BCD number
 Carry added to the most significant BCD digit
23 0010 0011
48 0100 1000
71 0110 1011
0110
0111 0001

31. Logic Gates
 Basic Building Blocks
 Logic Gate Symbol
 Unique function
 Truth or Function Table
 Function Expression
 Timing Diagram

32. AND Gate
 1 output
 2 inputs
 3 inputs
 4 inputs
 Multiple inputs

33. AND Gate function
Input Output
A B F
0 0 0
0 1 0
1 0 0
1 1 1
 Logical Multiplication function
BAF •= NCBAF ••••= ....

34. AND Gate Timing Diagram

35. OR Gate
 1 output
 2 inputs
 3 inputs
 4 inputs
 Multiple inputs

36. OR Gate function
Input Output
A B F
0 0 0
0 1 1
1 0 1
1 1 1
 Boolean Add function
BAF += NCBAF ++++= ..

37. OR Gate Timing Diagram

38. NOT Gate
 1 input
 1 output

39. NOT Gate function
Input Output
A F
0 1
1 0
 Invert function
AF =

40. NOT Gate Timing Diagram

41. AND Gate Applications
 Enable/Disable Device
 Counter counts when it receives pulses

42. NOT Gate Applications
 1’s Complement

43. Alternate Representations

44. NAND Gate
 1 output
 2 inputs
 3 inputs
 4 inputs
 Multiple inputs

45. NAND Gate function
Input Output
A B F
0 0 1
0 1 1
1 0 1
1 1 0
 NOT-AND function
BAF •= NCBAF ••••= ....

46. NAND Gate Timing Diagram
t0
t4
t5
t6
t1
t2
t3
A
B
F

47. NAND Universal Gate
Input Output
A B F
0 0 1
0 1 1
1 0 1
1 1 0

48. NAND Universal Gate
Input Output Output
A B F1 F
0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1

49. NAND Universal Gate
Input Output
A B F
0 0 0
0 1 1
1 0 1
1 1 1

50. NOR Gate
 1 output
 2 inputs
 3 inputs
 4 inputs
 Multiple inputs

51. NOR Gate function
Input Output
A B F
0 0 1
0 1 0
1 0 0
1 1 0
 NOT-OR function
BAF += NCBAF ++++= ....

52. NOR Gate Timing Diagram

53. Home work: NOR Universal Gate

54. Questions???

55. Thank You…