1. Low power techniques aim to reduce both dynamic and static/leakage power in integrated circuits. Dynamic power is reduced through techniques like lowering supply voltage and clock frequency, while leakage power is reduced by increasing transistor threshold voltage. 2. Power gating is a widely used technique that temporarily turns off unused circuit blocks to drastically reduce leakage power. It requires additional power switches and isolation cells to safely turn blocks on and off. 3. Multi-threshold CMOS uses both low and high threshold voltage transistors optimized for performance and leakage respectively. Further scaling presents new challenges as leakage power becomes dominant.

4. Power Has Broken the Rules of Scaling Cadence Design Systems Inc. estimates that 90-nm standard transistors are about 40 times leakier than the standard-voltage 130-nm transistors

6. Dynamic Power 0 to 1 on the output  charges the capacitive load of the PMOS 1 to 0 on the output  discharges the capacitive load through the NMOS Instantaneous rise time one transistor is ON at a time

10. To get equal rise/fall  balance transistor sizing Pavg(short circuit) = 1/12.k.τ.Fclk.(Vdd-2Vt)3 Short Circuit Power-Analysis If Vdd<Vthn+|Vthp| can we eliminate short circuit current????? Q Condition PMOS NMOS Vin < Vth ON (sat) OFF (cutoff) Vin = Vth Linear (towards cutoff) Linear (towards sat) Vin > Vth OFF (cutoff) ON (sat)

12. - does not depend on input transition, load capacitance -remains constant Leakage Power Contd....

13. Ireverse=A.Js.(e(q.Vbias/kT)-1) where, Vbias --> reverse bias voltage across the junction Js --> reverse saturartion current density A --> junction area How to reduce? Decrease in junction area  depends material Parasitic diodes formed between the diffusion region of the transistor and substrate Reverse Biased Diode Current (Junction Leakage)-I1 Can we adjust Vbias to control junction leakage? Q

14. Reverse Biased Diode Current (Junction Leakage)-I1 Contd…

20. Technology shrinking vs Leakage components 45 nm and below==>increased electric field==>increased gate leakage To counteract this voltage is scaled down to around 1V Other leakages are low due to improvements in the fabrication process and material.

21. Low Power Design Techniques Dynamic Power Leakage Power Design Architectural Process Technology Clock gating Multi Vt Multi Vt Pipelining Multi Vt Variable frequency Power gating Clock gating Asynchronous PD SOI Variable power supply Back (substrate) bias Power gating FD SOI Multi Vdd Use new devices-FinFet, SOI Multi Vdd FinFet Voltage islands DVFS Body Bias DVFS Multi oxide devices Minimize capacitance by custom design

22. Low Power Design Techniques Advanced techniques Basic techniques

23. Evolution of low power techniques Source: SNUG 2007

29. Different multi vt flows One (single) pass flow Two pass flow Compile with a set of libraries -Compile with a set of libraries -Incremental compilation with another set of libraries -Rvt-Lvt -Rvt-Hvt -Multi Vt -Lvt -Hvt -Lvt to Mvt -Hvt to Mvt -Rvt to Multi Vt

30. Low Vt to Multi-Vt -Least cell count -Good for tight timing constraint -Highest leakage power -Less opportunity for leakage optimization

31. High Vt to Multi-Vt -Least leakage power -Good for leakage critical design -Higher cell count With different timing constraints it works as well balanced flow High Vt library Low Vt library

32. Compile With Multi-Vt Libraries-Multi Vt One Pass Flow Overall good result Can be used for most of the designs

45. Header –Footer Switches A power switch ( header or footer ) is added to supply rails to shut-down logic (MTCMOS switches)

53. Some logic needs to stay active during shut-down 􀂃 Internal enable pins (ISO/ELS) 􀂃 Power switches 􀂃 Retention registers 􀂃 User-specific cells Always on logic

54. Low-Power Infrastructure Low-power design requires new cells with multiple power pins Additional modeling information in “.lib” is required to automatically handle these cells

56. Library syntax of special cells

58. Improvement in Process technology For 90nm and 65nm dielectric = 5 molecular layers thick ~ 1nm 25x reduction in gate leakage 5x reduction in sub threshold leakage

60. Tradeoffs

61. Tradeoffs Contd...

63. Carbon Nano tubes ??? Channel is a coil of carbon hexagons Mobility up to 70x silicon