Qing Jiang has over 15 years of experience in analog/mixed-signal/RF integrated circuit design. He has a M.Sc. in Condensed Matter Physics and has worked on projects including dual-band GNSS receivers, SERDES, ADCs/DACs, and timing controller ICs for LCD panels. His technical skills include design in deep submicron CMOS processes, analog/RF circuits, mixed-signal systems, and layout optimization.

1. Qing Jiang
416 Milner Ave., Scarborough, Toronto, M1B 1Z9, ON • (647) 469-8880 • jiangqing0033@gmail.com
PROFILE
 Analog/mixed-signal/RF integrated circuits designer with M.Sc. degree
 More than 15 years hands-on engineering experience in analog/mixed-signal/RF IC design , including 7 years in NEC
Electronics(now Renesas Electronics)
TECHNICAL SKILLS HIGHLIGHT
 Have solid analog/RF background, very experienced in RF & analog/mixed-signal design, especially in OPAMs, Bandgap,
Regulator, Comparator, PLL , LVDS, LNA, Mixer, VCO, Frequency Synthesizer, ADC/DAC, and SERDES in
CMOS/Bipolar process.
 Analytical and innovative-minded, excellent skills in problem solving, troubleshooting and bench debug
 Solid technical expertise over 10 years, successfully developed RF & analog/mixed-signal ICs with high challenges, such as
dual-band GNSS RF receivers, SERDES, ADC/DAC, Video & Audio AFE LSI.
 Familiar with deep submicron CMOS process (65nm), design tools (Cadence SpectreRF, HSPICE, Matlab).
 Ability to define chip level architecture, conduct chip level simulations for complicated mixed mode analog and RF systems
 Rich experience in layout effect to different kinds analog circuits, especially high speed and high resolution circuits.
 Familiar with lab measurement equipments, such as oscilloscope, spectrum analyzer, RF generator.
PROJECT EXPERIENCE
RF & analog/mixed-signal project lead Apr. 2007 –Dec. 2013
Beijing Kilosilicon Co., Ltd. Beijing, China
One chip design of the Dual-band GNSS RF Receiver
 Created architecture, defined chip-level and sub-block specification, communicated with customers
 Designed and simulated each block, finished top-chip integration, conducted top-chip simulation.
 Created evaluation proposal, evaluated and debugged the RF receiver.
 The RF chip integrated two channel receivers, for multimode compatible navigation. The low intermediate frequency scheme
was used, and it was designed in SMIC 0.18um CMOS process. I/Q two mixers were used for image-reject. The RF signal’s
frequency range extends from 1.2GHz to 1.6GHz.
 Main blocks include: LNA (pseudo-different), Mixer, LO (about 3.2GHz) with integer/fractional divider, PGA, Complex filter,
VGA, AGC (with amplitude detector), ADC, etc..
 The measured results: NF(the whole Receiver) is 4.5dB, PN(phase noise) is -98dBc at 100KHz, Image Rejection is 27dB,
Band Filter Rejection at 1.5 times of -3dB Bandwidth is 28dB, the maximum gain can reach 105dB, and the maximum
adjustable gain was about 65dB, chip power consumption is 90mW.
Serdes Design for Different Application
 Serdes for RapidIO 1.x, data rate 2.125Gbps in SMIC 0.13um/0.65um process. Included 2.125Gbps LVDS RX&TX,
1.0625GHz PLL, Bandgap, Regulator, etc
 In serdes, the clock phase can be adjusted by 10bit resolution, implemented by an analog circuit.
 Serdes for SG (Data interface between Servers), data rate 622Mbps in SMIC 0.13um process. Included 622Mbps LVDS
RX&TX, 622MHz PLL, Bandgap, Regulator, etc
66MHz 14bit pipeline ADC
 The pipeline ADC was designed from scratch, and circuits were designed through investigating paper.
Others
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2.  12GHz LC VCO, OCXO(Bipolar process)
Qing Jiang ( 647) 469-8880 • jiangqing0033@gmail.com
Analog/mixed-signal project lead Aug. 2005 –Feb. 2007
Beijing FineIC Co., Ltd. Beijing, China
The one chip design of Timing Controller IC(TCON) for 17’/19’ TFT LCD Panel
 Timing Controller IC(TCON) for 17’/19’ TFT LCD Panel in 0.18um process, supporting SXGA resolution, LVDS
RX(525MHz), Mini-LVDS TX(150MHz).
 Responsible for defining specification, creating design proposal, choosing process, designing circuits and layout,
evaluating and debugging chips. The mixed-signal IC was designed from scratch and the ES was successful for the first
time tape-out.
 Main Analog IP: 800MHz LVDS RX, 360MHz mini-LVDS transmitter. 500M PLL, DLL, Serdes, 150mA LDO, Bandgap
etc.
Analog/mixed-signal project lead Oct.1999–Jul.2005
Beijing NEC Integrated Circuits Co., Ltd. Beijing, China
PHS Base Band LSI
 The chip includes voice RX/TX, MOD, DEMOD, Phase Detection, etc. The analog blocks include a series of delta-sigma
ADC/DAC for voice RX/TX, 10bit SAR ADC, PLL(96MHz), REG, Bandgap, OSC,etc. It was designed in 0.15um CMOS
process.
 Responsible for defining specification, creating design proposal, designing circuits and layout, evaluating and debugging
chips.
CCD Analog Front End LSI for Signal Receiving used in digital camera in 0.35um CMOS Process
 Analog video signal process from CCD sensor, the analog blocks include CDS, GCA, OB clamp circuits, ADC and so on.
LSI for industrial application in 0.54um CMOS Process
 The analog blocks include 35ppm regulator, Power Supply, FSK receiver and transmitter, and so on. The 35ppm regulator,
16bit delta-sigma DAC.
STB LSI used for video signal process in 0.35u CMOS Process
 One analog AGC was implemented with innovation structure, in order to realize that gain(dB) linearized to the control
voltage, with 13MHz bandwidth. Besides AGC, some other analog macros(such as VBL, Bandgap, Regulator ) was also
designed.
Other Projects
 OCXO in bipolar process
 Rail-to-rail OPAMPs
 MCU regulator(Load current 120mA)
 A series of OPAMP, Comparator, Regulator, Bandgap IP designed in BiCMOS/Bipolar Process
EDUCATION AND TRAINING
 Training-on-work for Analog IC(BiCMOS) design technology in NEC Co., LTD, in Japan Feb.1999—Dec.1999
 Master of Science (M.Sc.)
Major in Condensed Matter Physics
Cryogenic Laboratory, Chinese Academy of Science, Beijing, China, Sept.1994--Jul. 1997
 Bachelor of Engineering (B.E.)
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3. Major in Automatic Engineering
Department of Electrical Engineering, Tongji University, Shanghai, China, Sept.1989--Jul. 1994
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