chapter 1

1. Digital Design
Lecture 1
Introduction to different type of
MSI’s devices

2.  This is a basic undergraduate course
designed to develop an insight into the
digital logic design. Key concepts that will
be learned are
̶ Logic Design
̶ MSI circuits
̶ Flip-flops
̶ VHDL
̶ Counters and registers
̶ Memory devices
̶ PLD

3.  A Digital Logic Gate is an electronic device
that makes logical decisions based on the
different combinations of digital signals
present on its inputs.
 Digital logic gates may have more than one
input, (A, B, C, etc.) but generally only have
one digital output, (Q).
 Individual logic gates can be connected
together to form combinational or sequential
circuits, or larger logic gate functions.

4.  Standard commercially available digital logic
gates are available in two basic families or
forms, TTL which stands for Transistor-
Transistor Logic such as the 7400 series,
and CMOS which stands for Complementary
Metal-Oxide-Silicon which is the 4000 series
of chips.
 This notation of TTL or CMOS refers to the
logic technology used to manufacture the
integrated circuit, (IC) or a “chip” as it is more
commonly called.

5.  Generally speaking, TTL logic IC’s use NPN
and PNP type Bipolar Junction Transistors
while CMOS logic IC’s use complementary
MOSFET or JFET type Field Effect Transistors
for both their input and output circuitry.
 As well as TTL and CMOS technology, simple
digital logic gates can also be made by
connecting together diodes, transistors and
resistors to produce RTL, Resistor-
Transistor logic gates, DTL, Diode-
Transistor logic gates

6.  Integrated Circuits or IC’s as they are more
commonly called, can be grouped together
into families according to the number of
transistors or “gates” that they contain.
 For example, a simple AND gate my contain
only a few individual transistors, were as a
more complex microprocessor may contain
many thousands of individual transistor
gates.

7.  Integrated circuits are categorised according
to the number of logic gates or the
complexity of the circuits within a single chip
with the general classification for the number
of individual gates given as: Small-Scale
Integration (SSI),
Medium-Scale Integration (MSI), Large Scale
Integration (LSI), Very Large Scale Integration
(VLSI), SLSI and Ultra-Large Scale Integration
(ULSI)

8.  Classification of Integrated Circuits
◦ Small Scale Integration or (SSI) – Contain up to 10
transistors or a few gates within a single package
such as AND, OR, NOT gates.
◦ Medium Scale Integration or (MSI) – between 10 and
100 transistors or tens of gates within a single
package and perform digital operations such as
adders, decoders, counters, flip-flops and
multiplexers.

9.  Classification of Integrated Circuits
◦ Large Scale Integration or (LSI) – between 100 and
1,000 transistors or hundreds of gates and
perform specific digital operations such as I/O
chips, memory, arithmetic and logic units.
◦ Very-Large Scale Integration or (VLSI) – between
1,000 and 10,000 transistors or thousands of
gates and perform computational operations such
as processors, large memory arrays and
programmable logic devices.

10.  Classification of Integrated Circuits
◦ Super-Large Scale Integration or (SLSI) – between
10,000 and 100,000 transistors within a single
package and perform computational operations
such as microprocessor chips, micro-controllers,
and calculators.
◦ Ultra-Large Scale Integration or (ULSI) – more than
1 million transistors – are used in computers
CPUs, GPUs, video processors, micro-controllers,
and FPGAs

11. • Multiplexers (Mux)
̶ 2x1, 4x1, and 8x1 muxes
̶ 74x151, 74x153, 74x157 devices
̶ Mux expansions
• Demultiplexers (Demux), Decoders, and Encoders
̶ 74x138 and 74x139 decoders
̶ Encoder, priority encoder and the 75x147 devices
̶ BCD to 7-segment decoder and the 74x247 devices
̶ Logic functions using muxes and decoders
• Adders and Comparators
̶ Half, full and ripple carry adders
̶ The 74x83 devices
̶ Comparator and the 74x85 devices

12. • MSI (Medium Scale Integrated) circuits are logic
circuits that contain 12 to 99 logic gates

13. • Its combinational circuit that selects binary
information from one of many input and
direct it to output line
• The particular data line that is selected is
determined by the select inputs.

14. • 2x1 Mux (2 input data and 1 output data)
̶ How to design a 2x1 mux using
basic gates?
 Using K-Map? What are the
inputs and outputs?
 By looking at its function?

15. • Design of 2x1 mux using K-Map
– Inputs: D0, D1, S
– Output: F

16. • Design of 2x1 mux by its function

17. How can we design the 4x1 mux using basic gates?
- Using K-Maps? What are the outputs and inputs?
- By its function?
• 4x1 mux

18. • The 4x1 Mux has six inputs (D3, D2, D1, D0, S1,
S0) and one output (F), therefore it is
difficult/time consuming to use K-Maps
Looking at the function of the 4x1 mux,
Therefore,
Can you implement this logic function?

20. • 8x1 mux

21. • Mux (and other common logic blocks) can be
bought as a packaged integrated circuits (IC)
• Commonly used IC is TTL and CMOS
• For example, an 2x1 mux IC in TTL is called
74LS157 (LS for Low Speed TTL)
• 2x1 mux IC in CMOS is called 74HC157 (HC for
High Speed CMOS)
• 2x1 Mux IC: 74LS157 (TTL)/74HC157 (CMOS)
• 4x1 Mux IC: 74LS153 (TTL)/74HC153 (CMOS)
• 8x1 Mux IC: 74LS151 (TTL)/74HC151 (CMOS)

22. INPUT
◦ 8 input lines for data
◦ 3 high SELECT inputs (as
there are 8 input lines)
◦ EN input for expanding
purposes
OUTPUT
◦ 2 output lines (Z and Z’)

23. • Smaller multiplexers can be expanded to
obtain larger multiplexers
• Example 2: Design a 16x1 mux using two
74x151 IC’s and basic gates

25. Demultiplexers (Demux), Decoders, and
Encoders

26. o Reverse of the multiplexing function
o Takes data from one line and distributes to
a given number of output lines
o Demux can be designed as 1x2, 1x4, 1x8,
etc.

27. o 1x2 Demux
Function:
D0 = D, D1 = 0 when S = 0
D1 = D, D0 = 0 when S = 1 D0 = D ∙ 𝑆
D1 = D ∙ S

28. o 1x4 Demux
𝐷0= D ∙ 𝑆1 ∙ 𝑆0
𝐷1= D ∙ 𝑆1 ∙ 𝑆0
𝐷2= D ∙ 𝑆1∙ 𝑆0
𝐷3= D ∙ 𝑆1 ∙ 𝑆0
Can you draw the logic circuit?
Data at D is distributed to D0 to D3 depending on select S1 and S0

30. o Detect the presence of a specified
combination of bits (code) on its inputs
and to indicate the presence of that code
by a specified output level
o Standard decoders are designed as 1x2,
2x4, 3x8, 4x16, etc
o Other decoders include the BCD to 7-
segment LED decoder, gray code
decoder, etc.

31. o 2x4 Decoder: only one output is active at one time
Active high output decoder
Function:

32. o Decoders are typically designed as active low
Bubble at output denotes active low output
Function:
O3O2O1O0 = 1110 when A1A0 = 00 O3O2O1O0 =
1101 when A1A0 = 01 O3O2O1O0 = 1011 when
A1A0 = 10 O3O2O1O0 = 0111 when A1A0 = 11
𝑂0= 𝐴1 + 𝐴0
𝑂1= 𝐴1 + 𝐴0
𝑂2= 𝐴1 + 𝐴0
𝑂3= 𝐴1 + 𝐴0

34. o 3x8 Decoder
Function:
O7O6O5O4O3O2O1O0 = 1111 1110 when A2A1A0 = 000
O7O6O5O4O3O2O1O0 = 1111 1101 when A2A1A0 = 001
O7O6O5O4O3O2O1O0 = 1111 1011 when A2A1A0 = 010
O7O6O5O4O3O2O1O0 = 1111 0111 when A2A1A0 = 011
O7O6O5O4O3O2O1O0 = 1110 1111 when A2A1A0 = 100
O7O6O5O4O3O2O1O0 = 1101 1111 when A2A1A0 = 101
O7O6O5O4O3O2O1O0 = 1011 1111 when A2A1A0 = 110
O7O6O5O4O3O2O1O0 = 0111 1111 when A2A1A0 = 111
How does the logic circuit looks like?
- Can we use K-Map?

36. o Decoder IC’s
̶ 2x4 Decoder → 74139
̶ 3x8 Decoder → 74138

37. o 74247 BCD to 7 Segment Decoder
Converts 4-bit BCD (A3, A2, A1, A0) to 7-segment LED
(a,b,c,d,e,f,g)
Input: A3, A2, A1, A0
Control Input: LT, RBI, RBO
Output: a, b, c, d, e, f, g
** note that output is active low

38. o What is the output of 74247 if input
(A3A2A1A0)=0110?

39. o What is the output of 74247 if
input (A3A2A1A0)=0011?

42. o Performs reverse decoder function
o Only one input can be active at one time
Function:
A1A0 = 00 when D3D2D1D0 = 1110 A1A0 = 01
when D3D2D1D0 = 1101 A1A0 = 10 when
D3D2D1D0 = 1011 A1A0 = 11 when D3D2D1D0 =
0111
Which implies,
What happens if more than one input is ‘0’ (D0 = 0 and D1 = 0)?
- output is invalid, we need a priority encoder
𝐴1= 𝐷3𝐷2𝐷1𝐷0 + 𝐷3𝐷2𝐷1𝐷0
𝐴0= 𝐷3𝐷2𝐷1
𝐷0 + 𝐷3𝐷2𝐷1𝐷0

43. o Priority Encoder: Output depends on the largest active
input
4x2 Priority Encoder Function:
A1A0 = 00 when D3D2D1D0 = 1110 A1A0 =
01 when D3D2D1D0 = 110x A1A0 = 10
when D3D2D1D0 = 10xx A1A0 = 11 when
D3D2D1D0 = 0xxx
Can you derive the truth table of the priority encoder?
What happens if more than 1 input is ‘0’ (D0 = 0 and D1 = 0)?
- output A1A0 = 01

46. o Any logic function (AND, OR, decoder,
encoder, etc) can be realized using mux. All we
need is a truth table
o This is the concept widely being used today in
FPGA (Field Programmable Gate Array), where
any logic functions can be rapidly
implemented using Mux

47. o 2-input AND gate using 4x1 Mux

48. o Implement the following using Mux

49. o Similar to Mux, any logic function can be
realized using decoders
o 2-input AND gate using 2x4 decoder

50. o Implement the following using 74138

51. o Logic function of decoders can also be
implemented using a NAND gate