Introducing the CrossLink Programmable ASSP
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Lattice has introduced its CrossLink™ programmable bridging device that supports leading protocols for mobile image sensors and displays. Systems with embedded cameras and displays often do not have the right type or number of interfaces, which can be resolved using a bridge. The new CrossLink device combines the flexibility and fast time to market of an FPGA with the power and functional optimization of an ASSP to create a new product class called programmable ASSP (pASSP™).
![Lattice
Semiconductor[2]
Lattice Semiconductor
Company at a Glance
HQ:
Headquarters
DC:
Development Ctr.
OC:
Operations Ctr.
GLOBAL PRESENCE
Enabling processing and connectivity applications where time-to-
market, low power, and small size are critical.
CONSUMER INDUSTRIAL &
AUTOMOTIVE
COMMUNICATIONS
& COMPUTING
PROGRAMMABLE
LOGIC
VIDEO
CONNECTIVITY mmWave
MARKETS & PRODUCTS STRONG FINANCIALS
$406M
2015 Revenue
Consistent double-digit
revenue growth
2 BILLION +
Devices sold by
Lattice in the last 10
years
NASDAQ:
LSCC
IPO 1989
Founded
1983
2015
Acquired Silicon Image
for ~$600M
HISTORY OF INNOVATION
1992
ispCPLD
2003
HDMI
2004
SiBEAM 2006
Lattice
ECP2M
2011
Acquired
SiliconBlue for
~$62M
iCE65](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
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Introducing the CrossLink Programmable ASSP
- 2. Lattice Semiconductor[2] Lattice Semiconductor Company at a Glance HQ: Headquarters DC: Development Ctr. OC: Operations Ctr. GLOBAL PRESENCE Enabling processing and connectivity applications where time-to- market, low power, and small size are critical. CONSUMER INDUSTRIAL & AUTOMOTIVE COMMUNICATIONS & COMPUTING PROGRAMMABLE LOGIC VIDEO CONNECTIVITY mmWave MARKETS & PRODUCTS STRONG FINANCIALS $406M 2015 Revenue Consistent double-digit revenue growth 2 BILLION + Devices sold by Lattice in the last 10 years NASDAQ: LSCC IPO 1989 Founded 1983 2015 Acquired Silicon Image for ~$600M HISTORY OF INNOVATION 1992 ispCPLD 2003 HDMI 2004 SiBEAM 2006 Lattice ECP2M 2011 Acquired SiliconBlue for ~$62M iCE65
- 3. Lattice Semiconductor[3] Lattice Helps Connect the World Connect Everything to Anything….
- 4. Lattice Semiconductor[4] pASSPFPGAs ASIC / ASSPs Cost The pASSP Continuum Delivering the Best of Both Worlds
- 5. Lattice Semiconductor[5] D-PHY D-PHY MOBILE PROCESSOR D-PHY MCU APPLICATION PROCESSOR SPI D-PHY D-PHY DUAL D-PHY DISPLAY DISPLAY DSLR PROCESSOR Sub-LVDSIMAGE SENSOR D-PHY Lattice Solves Internal Device Connectivity Issues Chip-to-chip, Embedded Video Bridging For Cameras and Displays Insufficient inputs Insufficient outputs Incompatible outputsIncompatible inputs RightEyeLeftEye
- 6. Lattice Semiconductor[6] Lattice Solves Internal Device Connectivity Issues The ONLY Completely Customizable Video Bridge For Mobility MOBILE PROCESSOR MCU APPLICATION PROCESSOR SPI D-PHY D-PHY DUAL D-PHY DISPLAY DISPLAY DSLR PROCESSOR Camera aggregator bridge Display aggregator bridge Display interface bridgeCamera interface bridge D-PHY D-PHY D-PHY D-PHY Sub-LVDSIMAGE SENSOR RightEyeLeftEye
- 7. Lattice Semiconductor[7] CrossLink Device’s Features First programmable ASSP (pASSP) interface IC bridge supporting leading protocols for mobile image sensors and displays World’s fastest MIPI D-PHY bridging IC delivering up to 4K UHD resolution at 12 Gbps bandwidth Supports popular mobile, camera, display and legacy interfaces Industry’s smallest package size with a 6 mm2 option Lowest power programmable bridging solution in active mode Built-in sleep mode Combines the flexibility and fast time to market of an FPGA with the power and functional optimization of an ASSP to create a new product class called programmable ASSP (pASSP)
- 8. Lattice Semiconductor[8] Fastest Time to Market ASSP Benefits with FPGA Programmability Quicker Time to Market Develop and make design corrections in real time Create new use cases as they develop Same Low Power Optimized RTL for the use case Same Behavior One-time programmable NVCM technology Smaller Form Factor WLCS and flip chip packages Same Low Cost Number of pins dictates product cost, not FPGA logic vs. gates 1X
- 9. Lattice Semiconductor[9] Highest Level of Flexibility Programmability Increases Interface and Design Options Display Interface Protocols MIPI DSI to MIPI DSI MIPI DSI to Dual DSI Dual MIPI DSI to Dual MIPI DSI MIPI DSI to OpenLDI/LVDS MIPI DSI to MIPI DPI Single OpenLDI/LVDS to MIPI DSI MIPI DPI to MIPI DSI IPs available NOW Camera Interface Protocols Dual MIPI CSI-2 to MIPI CSI-2 MIPI CSI-2 to Parallel CMOS Parallel CMOS to MIPI CSI-2 SubLVDS to MIPI CSI-2
- 10. Lattice Semiconductor[10] Fastest MIPI D-PHY Bridging Solution 4K UHD Resolution at Speeds Up to 12 Gbps – 50% Higher IO Performance
- 11. Lattice Semiconductor[11] Smallest Form Factor 2x – 3x Smaller Footprint Than the Competition – As Small as 6 mm2 36 WLCSP 64 ucfBGA 81 csfBGA 80 ctfBGA 0.4 mm pitch 0.4 mm pitch 0.5 mm pitch 0.65 mm pitch 2.46 x 2.46 mm 3.5 x 3.5 mm 4.5 x 4.5 mm 6.5 x 6.5 mm 36 WLCSP 80 ctfBGA
- 12. Lattice Semiconductor[12] Lowest Power 100 mW Active. 25 – 50% Lower Power Than the Competition CrossLink Competitor 2 Competitor 3 0 50 100 150 200 250 Power(mW) Competitor 1 Competitor 2 Competitor 3 CrossLink Bridging Functions Competitor 1
- 13. Lattice Semiconductor[13] CrossLink Block Diagram Most Flexible Video Bridging Device Available Programmable IO RX: D-PHY / SubLVDS / LVDS / SLVS200 / CMOS TX: LVDS / CMOS 1.2 Gbps/Lane 14 IO / 7 Pairs MIPI D-PHY 6 Gbps RX & TX 4 data lanes 1 clock lane MIPI D-PHY 6 Gbps RX & TX 4 data lanes 1 clock lane GPIOs I2C/SPI Programmable FPGA Fabric 5,936 LUTs 180 kbits block RAM 47 kbits distributed RAM Enough FPGA resources to handle video: Muxing Merging Demuxing Arbitration Splitting Data conversion Custom Protocol Design Programmable IO RX: D-PHY / SubLVDS / LVDS / SLVS200 / CMOS TX: LVDS / CMOS 1.2 Gbps/Lane 16 IO / 8 Pairs Power Management Unit CrossLink
- 14. Lattice Semiconductor[14] Multi CSI-2 Bridge For Camera Image Processor D-PHYx4RX 1.2Gbps/lane D-PHYx4RX 1.2Gbps/lane D-PHYTXx4 @1.5Gbps Cntrl GEARING Mux/Merge RST Config SPI/I2C image sensor LineBuffer GEARINGLOGIC GEARING LineBuffer Trigger Image Sensor Control Trigger Image Sensor Controlimage sensor I2C Slave to Multi- Master I2C OSC CrossLink CSI-2 Solves Multi Image Sensor Latency Issues CSI-2 CSI-2
- 15. Lattice Semiconductor[15] 1:2 Dual MIPI DSI Bridge for Display Left Eye Right Eye D-PHYTX 1.5Gbps/lane D-PHYTX 1.5Gbps/lane RXx4D-PHY(soft)on 1.2GbpsPdiffIOphysical RST Config SPI/I2CREFCLK(Optional)PLL 1:16GEARING Application Processor Power Management Split Function CrossLink Solves AP Port Limitations DSI DSI DSI
- 16. Lattice Semiconductor[16] DSI RGB to MIPI DSI Display Bridge X4D-PHYTX @1.5Gbps/lane Pixeltobyte PLL De-packetize TXcontroller CMOS to D-PHY LP_D0 D_0 D_1 D_2 D_3 LP_CLK V_Sync H_Sync Pixel_Clk Pixel_Data Application Processor Display Solves AP and Display Interface Mismatches CrossLink
- 17. Lattice Semiconductor[17] Target Markets & Applications Any End Product Using Image Sensors or Displays DSC / DSLRWearables Smartphones Tablets Mobile Drones Traditional Machine Vision Surveillance Medical Handheld Equipment EBOOK
- 18. Lattice Semiconductor[18] Most Flexible - Supports popular mobile, camera, display and legacy interfaces Smallest package size – 6 mm2 option Lowest power programmable bridging solution in active mode Built-in sleep mode Ideal for virtual reality headsets, drones, smartphones, tablets, DSLR cameras, and wearable devices Takes the strongest features from ASSPs and FPGAs to deliver the best solution of both worlds CrossLink evaluation boards are available now from Lattice and its distributors and production devices will be available shortly CrossLink Device World’s Fastest MIPI D-PHY Bridging IC
- 19. Lattice Semiconductor[19] As communications become more mobile, and more of the world’s “things” talk with each other in increasingly complex ways, we will be the undisputed global leader for Smart Connectivity Solutions For more information visit: http://www.latticesemi.com/CrossLink
Notas do Editor
- 2004 – SiBEAM founded HQ: Portland, OR DC: - Hillsboro, OR San Jose, CA Shanghai, China Manila, Philippines Hyderabad, India OC: Manila, Philippines Singapore
- 3
- TECHNICAL DIAGRAMS - CHIP LAYOUT
- VR headset, hi res tablet
- Hand-held industrial
- Make 2+2