Karthik Rathinavel

cadence adc system verilog s parameters ads low pass filter modulator delta sigma matlab simulink decimation filter seven segment display uart altera fpga counter count display debouncing of buttons pwm control state machine sine wave generator low noise amplifier biasing lna em simulations layout wilkinson combiner op-amp design folded cascode telescopic op-amp fully differential switched capacitor differential input to single ended output op-amp tow-thomas-biquads matlab