Final report - 20th June.docx

The Faculty of Engineering and Technology
Department of Electronics and Communication Engineering
JAIN (Deemed-to-be University), Kanakapura Taluk-562112,
Ramanagara District, Karnataka, India
2018-2022
A Project Report on
“Design of Reversible Full Adder Using Gate Diffusion
Input”
Submitted in partial fulfilment for the award of the degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted by
KOPPERLA YOGESWAR REDDY
18BTREC031
S. MAHAMMAD HUSSAIN
18BTREC090
SHOROFF VAMSHI KRISHNA
18BTREC091
KARICHETI MANIKANTA
18BTREC093
Under the guidance of
Dr. Hamsa S
Assistant Professor
Department of Electronics and Communication Engineering
Faculty of Engineering & Technology (FET)
JAIN (Deemed-to-be University)

Faculty of Engineering & Technology (FET)
Department of Electronics & Communication Engineering
JAIN (Deemed-to-be University)
Kanakapura Taluk-562112
Ramanagara District
Karnataka, India
CERTIFICATE
This is to certify that the project work titled “Design of Reversible Full Adder
using Gate Diffusion Input" is carried out by KARICHETI
MANIKANTA(18BTREC093), KOPPERLA YOGESWAR REDDY(18BTREC031),
S.MAHAMMAD HUSSAIN (18BTREC090), SHOROFF VAMSHI
KRISHNA(18BTREC091), are bonafide students of Bachelor of Technology at the
Faculty of Engineering & Technology, JAIN DEEMED-TO-BE UNIVERSITY,
Bengaluru in partial fulfilment for the award of a degree in Bachelor of Technology in
Electronics and Communication Engineering, during the year 2021-2022
Dr. Hamsa S Dr. R. Sukumar Dr. Hariprasad S.A
Assistant Professor
Dept. of ECE,
Faculty of Engineering & Technology,
JAIN DEEMED-TO-BE UNIVERSITY
Date:
Head of the Department,
Electronics and Communication,
Date:
Director,
Date:
The Name of the Examiner Signature of Examiner
1.
2.

i
<
DECLARATION
We, Kopperla Yogeswar Reddy (18BTREC031), S.Mahammad Hussain (18BTREC090),
Shoroff Vamshi Krishna (18BTREC091), and Karicheti Manikanta (18BTREC093) are
students of eighth semester B.Tech in Electronics and Communication Engineering , at
Faculty of Engineering & Technology, JAIN (Deemed-to-be university) , hereby declare that
the project titled “Design of Reversible Full Adder using Gate Diffusion Input” has been
carried out by us and submitted in partial fulfilment for the award of a degree in Bachelor of
Technology in Electronics and Communication Engineering during the academic year
2021-2022. Further, the matter presented in the project has not been submitted previously by
anybody for the award of any degree or any diploma to any other university, to the best of our
knowledge and faith.
Signature
Kopperla Yogeswar Reddy
18BTREC031
S.Mahammad Hussain
18BTREC090
Shoroff Vamshi Krishna
18BTREC091
Karicheti Manikanta
18BTREC093
Place : Bengaluru
Date:

ii
ACKNOWLEDGEMENT
It is a great pleasure for us to acknowledge the assistance and support of a large number of
individuals who have been responsible for the successful completion of this project work.
First, we take this opportunity to express our sincere gratitude to Faculty of Engineering &
Technology, JAIN (Deemed-to-be University) for providing us with a great opportunity to
pursue our Bachelor’s Degree in this institution.
In particular we would like to thank Dr. Hari prasad S.A, Director, Faculty of Engineering
& Technology, JAIN (Deemed-to-be University) for his constant encouragement and expert
advice.
It is a matter of immense pleasure to express our sincere thanks to Dr. R. Sukumar, Head of
the department, Electronics and Communication Engineering, JAIN (Deemed-to-be
University), for providing right academic guidance that made our task possible.
We would like to thank our guide Dr. Hamsa S, Assistant Professor, Dept. of Electronics and
Communication Engineering, JAIN (Deemed-to-be University), for sparing his valuable
time to extend help in every step of our project work, which paved the way for smooth progress
and fruitful culmination of the project.
We would like to thank our Project Coordinator Mr. Sunil M P and all the staff members of
Electronics and Communication for their support.
We are also grateful to our family and friends who provided us with every requirement
throughout the course. We would like to thank one and all who directly or indirectly helped us
in completing the Project work successfully.
Signature of Students
Karicheti Manikanta Shoroff Vamshi Krishna
Kopperla Yogeswar Reddy S. Mahammad Hussain

iii
ABSTRACT
In VLSI designs today, the device dimensions are shrinking exponentially and the
circuit complexity is also growing exponentially. Further, device scaling is limited by the
power dissipation, which calls for better power optimization methods. Reversible Logic is
becoming a more and more prominent special optimization technique, having its
applications in Low Power CMOS designs, Quantum Computing, Nanotechnology, and
Optical Computing. Reversibility plays an important role when energy efficient
computations are to be designed. Addition is a vital arithmetic operation and acts as a
building block for synthesizing all other operations. A high-performance adder is one of
the key components in the design of application specific integrated circuits. In our design,
the full adder is designed using Peres gates. Peres gates offer the advantage of low quantum
cost, low garbage output. GDI is a low power design technique that offers the
implementation of the logic function with fewer transistors. This technique allows the
minimization of area and power consumption of digital circuits.
The GDI technique allows the minimization of area and power consumption of
digital circuits. The reversible gate preserves the same parity between output and input
vectors. In this design, the Peres Gate is designed using Gate Diffusion Input using 8
transistors. The proposed new Peres Gate is used to design a full adder with power
efficiency. In this work, a power consumption of 51.62W is achieved for supply voltage of
1V and the total area is 492μm2. The schematic is designed in Tanner EDA.
Keywords: Peres Gate, Reversible Logic Gate, Low Power, Gate Diffusion Input (GDI),
Full Adder, 45 nm Technology.

iv
TABLE OF CONTENTS
List of Figures vi
List of Tables vii
Chapter 1 1
1. INTRODUCTION 1
1.1 Literature Survey 2
1.2 Limitations of the Current Work 5
1.3 Problem Definition 6
1.4 Objectives 7
1.5 Methodology 7
1.6 Hardware and Software tools used 8
Chapter 2 9
2. BASIC THEORY 9
2.1 Adders 9
2.2 Reversible logic gates 10
2.3 Types of Reversible logic gates 11
2.4 Gate Diffusion Input 14
Chapter 3 16
3. TOOL DESCRIPTION 16
Chapter 4 33
4. IMPLEMENTATION 33
Chapter 5 36
5. RESULTS AND DISCUSSION 36
CONCLUSIONS AND FUTURE SCOPE 41
REFERENCES vii

v
APPENDICES ix
APPENDIX-I ix
INFORMATION REGARDING STUDENTS xii
BATCH PHOTOGRAPH ALONG WITH GUIDE xiii

v
LIST OF FIGURES
Fig. No. Description of the figure Page No.
1.5.1
Block diagram of Full Adder using Peres gate
8
2.1.1 Block diagram of Full adder 9
2.1.2 Block diagram of Full Adder using logic gates 10
2.3.1 Block diagram of Feynman Gate 11
2.3.2 Block diagram of Fredkin Gate 12
2.3.3 Block diagram of Peres Gate 13
2.4.1
Gate Diffusion Input (GDI) cell
14
3.1.1
Parts of the User Interface
16
3.1.2
Standard Toolbar
17
3.1.3
Usage of Tanner Tool
18
3.1.4
Customizing Toolbar
19
3.1.5
Commands Tab
20
3.1.6
Adding a New Menu
20
3.1.7
Start Tanner
21
3.1.8
New design
22
3.1.9
To create a New Libraries
22
3.1.10
To create a New Cell
23
3.1.11
To select a New Design
24
3.1.12
To make Circuit Schematic
24
4.1
Schematic of Existing Full Adder
33
4.2 2T AND gate using GDI technology 33

v
4.3 3T XOR gate using GDI technology 34
4.4 Peres gate using GDI technology 34
4.5 Full Adder using modified Peres gate 35
5.1 Output waveform of Existing Full Adder 36
5.2 Output waveform of 2T AND gate using GDI 36
5.3 Output waveform of 3T xor gate using GDI 37
5.4 Output waveform of modified Peres gate 37
5.5 Output waveform of Full adder using Modified Peres gate 38
5.6 Area of Existing Full Adder 38
5.7 Average power of Existing Full Adder 38
5.8 Delay of Existing Full Adder 39
5.9 Area of modified Full adder 39
5.10 Average power of modified Full adder 39
5.11 Delay of modified Full adder 40
LIST OF TABLES
Table No. Description of the Table Page No.
2.1.1 Truth table of Full adder 9
2.3.1 Truth table of Feynman gate 11
2.3.2 Truth table of Fredkin gate 12
2.3.3 Truth table of Peres gate 13
5.1
Comparison between existing Full adder and Modified Full
adder. 40

Design of Reversible Full adder using Gate Diffusion Input
Department of Electronics and Communication Engineering, FET, JAIN (DEEMED-TO-BE-UNIVERSITY) 1
Chapter 1
1. Introduction
In VLSI digital circuits, power and area reduction is the important parameter which decides the
efficiency of the circuit [1]. Power consumption is the primary factor in high performance
computing application, Image processing applications. The author R. Landauer has said that to
compute irreversible logic, kTln2 joules of heat energy generates per bit information lost [2]. The
author Bennett said that by using reversible logic can eliminate of kTln2 energy dissipation. Another
one design technique known as Gate Diffusion Input (GDI) style that replaces CMOS logic and it
was developed for fabrication in SoI and twin-well CMOS process.
Another one design technique known as Gate Diffusion Input (GDI) style that replaces CMOS logic
and it was developed for fabrication in SOI and twin-well CMOS process. “In VLSI digital circuits,
power and area reduction is the important parameter which decides the efficiency of the circuit.
Power consumption is the primary factor in high performance computing applications, Image
processing applications. Circuits like adders, subtractors, comparators are used for computational
purpose in processors which are used in mobile and laptops. Adders are digital circuits that carry
out addition of numbers.
Adders are a key component of the Arithmetic Logic unit. Adders can be constructed for most of
the numerical representations like Binary Coded Decimal, Gray code, Binary etc. out of these,
binary addition is the most frequently performed task by most common adders. Apart from addition,
adders are also used in certain digital applications like table index calculation, address decoding etc.
.
The GDI approach allows implementation of a wide range of complex logic functions using only
two transistors. This method is suitable for design of fast, low-power circuits, using a reduced
number of transistors (as compared to CMOS and existing PTL techniques) The inputs and outputs
of reversible logic gates can be uniquely retrievable from each other. The reversible logic operations
can’t erase information and dissipate zero heat. The circuit actually operates in a backward
operation, allows reproducing the inputs from the outputs and consumes zero power. The first VLSI
circuits, produced in the 1970s, contained a small number (by today’s standards) of devices and
consequently an acceptably low average number of defects per chip.

Adders are heart of computational circuits.it is used in many combinational and application based
integrated circuits. In processors, full adder circuits are substantially used in reckoning architectures
like Arithmetic logic units, Digital signal processors, Counters, Image processing, etc. Total power
expenditure, Size and propagation delay are the dominating factors to analyse the realization of
these processors. Hence, the focus has been to optimize these necessities. As CMOS technology
scaling continuous in to the Nano scale domain, the density of transistors embedded in to a single
chip also increased. Reversible computing is one of the innovative method in low power dissipating
circuit design for cryptography, thermodynamics to reduce the power dissipation by eliminating
information loss.
1.1 Literature Survey
Somashekhar Malipatil, Vikas Maheshwari, and Marepally Bhanu Chandra, “Area
Optimization of CMOS Full Adder Design Using 3T XOR”, 978-1-7281-5284- 4/20/$31.00 ̹
2020 IEEE.
GDI (Gate Diffusion Input) is a new technique of low power digital circuit design is proposed. This
technique allows minimization of area and power consumption of digital circuits. In this design
XOR gate is designed using 3 transistors and CMOS full adder is designed based on two 3T XOR
and one 2T Mux. Using 8 transistors the full adder is designed in this paper and voltage scaling also
done by reducing supply voltage. In this proposed full adder, the power consumption 4.604μW is
achieved and the total area is 144μm 2
.
Keywords: Adders, Transistors, Logic gates, Power demand, CMOS technology, Three-
dimensional displays, Digital circuits.
Summary: The proposed design of this project will shows the power consumption 4.604μW is
achieved and the total area is 144μm 2
.
R. Landauer, “Irreversibility and Heat Generation in the Computational Process”, IBM
Journal of Research and Development, 5, pp. 183-191, 1961.
It is argued that computing machines inevitably involve devices which perform logical functions
that do not have a single-valued inverse. This logical irreversibility is associated with physical
irreversibility and requires a minimal heat generation, per machine cycle, typically of the order of
kT for each irreversible function. This dissipation serves the purpose of standardizing signals and
making them independent of their exact logical history. Two simple, but representative, models of
bi stable devices are subjected to a more detailed analysis of switching kinetics to yield the

relationship between speed and energy dissipation, and to estimate the effects of errors induced by
thermal fluctuations.
Keywords: Bit line leakage current, Transistors, Logic gates, Power demand.
Summary: This dissipation serves the purpose of standardizing signals and making them
independent of their exact logical history.
C.H Bennett “Logical Reversibility of computations” IBM J. Research and development, pp 525-
532, November1973.
The usual general-purpose computing automaton (e.g.. a Turing machine) is logically irreversible-
its transition function lacks a single-valued inverse. Here it is shown that such machines may he
made logically reversible at every step, while retaining their simplicity and their ability to do general
computations. This result is of great physical interest because it makes plausible the existence of
thermodynamically reversible computers which could perform useful computations at useful speed
while dissipating considerably less than kT of energy per logical step. In the first stage of its
computation the logically reversible automaton parallels the corresponding irreversible automaton,
except that it saves all intermediate results, thereby avoiding the irreversible operation of erasure.
The second stage consists of printing out the desired output. The third stage then reversibly disposes
of all the undesired intermediate results by retracing the steps of the first stage in backward order (a
process which is only possible because the first stage has been carried out reversibly), thereby
restoring the machine (except for the now-written output tape) to its original condition. The final
machine configuration thus contains the desired output and a reconstructed copy of the input, but
no other undesired data. The foregoing results are demonstrated explicitly using a type of three-tape
Turing machine. The biosynthesis of messenger RNA is discussed as a physical example of
reversible computation.
Keywords: CMOS technology, Three-dimensional displays, Digital circuits.
Summary: The final machine configuration thus contains the desired output and a reconstructed
copy of the input, but no other undesired data. The foregoing results are demonstrated explicitly
using a type of three-tape Turing machine.
A. Morgenshtein et al., "Gate-diffusion input (GDI) - a technique for low power design of
digital circuits: analysis and characterization," 2002 IEEE International Symposium on
Circuits and Systems. Proceedings.
GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is described. This

technique allows reducing power consumption, delay and area of digital circuits, while maintaining
low complexity of logic design. Performance comparison with traditional CMOS and various PTL
design techniques is presented, with respect to the layout area, number of devices, delay and power
dissipation, showing advantages and drawbacks of GDI as compared to other methods. A variety of
logic gates have been implemented in 0.35 /spl mu/m technology to compare the GDI technique
with CMOS and PTL. A prototype test chip of 8-bit CLA adder has been fabricated, based on GDI
and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI. Properties
of implemented circuits are discussed, simulation results are reported and measurements of a test
chip are presented.
Keywords: CMOS technology, Energy consumption, Three-dimensional displays, Digital circuits.
Summary: In this project the Performance comparison with traditional CMOS and various PTL
design techniques is presented, with respect to the layout area, number of devices, delay and power
dissipation, showing advantages and drawbacks of GDI as compared to other methods.
A. Peres, “Reversible logic and quantum computers”, Physical Review: A, vol. 32, no. 6, pp.
3266-3276, 1985.
This article is concerned with the construction of a quantum-mechanical Hamiltonian describing a
computer. This Hamiltonian generates a dynamical evolution which mimics a sequence of
elementary logical steps. This can be achieved if each logical step is locally reversible (global
reversibility is insufficient). Computational errors due to noise can be corrected by means of
redundancy. In particular, reversible error-correcting codes can be embedded in the Hamiltonian
itself. An estimate is given for the minimum amount of entropy which must be dissipated at a given
noise level and tolerated error rate.
Keywords: CMOS technology, Energy consumption, Three-dimensional displays, Digital circuits,
GDI.
Summary: Reversible error-correcting codes can be embedded in the Hamiltonian itself. An
estimate is given for the minimum amount of entropy which must be dissipated at a given noise
level and tolerated error rate.
S. Hiremath, A. Mathad, A. Hosur and D. Koppad, "Design of low power standard cells using
full swing gate diffusion input," 2017 International Conference On Smart Technologies For
Smart Nation (SmartTechCon), Bangalore, 2017, pp. 940-945, doi:
10.1109/SmartTechCon.2017.8358510.

The key success factor for the rapid growth of the integrated system is the use of ASIC library for
various system functions. Different Integrated Circuits (IC) implementation approaches have been
used to reduce the design time and improve manufacturing costs. One of the method is designing
Cell Based IC implementation approach using standard cell libraries. The performance of the design
is depends on the quality of standard cells used in the design. Hence designing low power, high
speed standard cells plays an imported role in the system design. In this paper standard cells are
created using Gate Diffusion Input (GDI) technique which gives better result than CMOS standard
cells in terms of power, area and delay. The standard cells are characterized using Liberate tool from
the Cadence and used in full adder design using Verilog code. Comparing the CMOS and GDI
standard cells result in terms of power, area and delay.
Keywords: Logic gates, Standards, Transistors, Libraries, MOS devices, Delays, Adders.
Summary: The performance of proposed design is depends on the quality of standard cells used in
the design. Hence designing low power, high speed standard cells plays an imported role in the
system design. In this paper standard cells are created using Gate Diffusion Input (GDI) technique
which gives better result than CMOS standard cells in terms of power, area and delay.
1.2 Limitations of the current work
EXISTING FULL ADDER TECHNOLOGIES
A rapid growth is being observed in the area of Integrated Circuits (IC) technology. All the ICs are
to be designed in an optimized way so that they meet all the requirements of being faster, occupying
less area and reduced power consumption. One of the circuits which occupy most of ICs is ALU
which is a combination of arithmetic and logic units. Of the arithmetic units two are most important
which are the adders and multipliers. This paper describes an efficient method to design full adders
which is the basic unit of adders in ALUs.
Nowadays all the systems are built on an upcoming technology called System on Chip (SoC) in
which all the components and peripherals have been built on a single chip which increases the
complexity of the system. VLSI plays an important role in the development of such ideas.
Initially the electronics started their evolution with the invention of vacuum tubes. But with the help
of Vacuum tubes only the movement of electrons were studied. After vacuum tubes transistors and
diodes were introduced. But for larger circuits it was difficult to fabricate them in a board as they

occupied larger space and consumed more power. Also it was difficult for the designers to identify
the wiring and routing faults which occurred in such circuits. This led to the invention of Integrated
Circuits by Jack and Kilby in which more number of transistors were integrated on a single chip.
Initially 3 to 30 transistors were fabricated in a single chip which is known as Small Scale
Integration (SSI). Then about 30 to 300 transistors were developed in a single chip which is known
as Medium Scale Integration. All the above events happened in 1940S.
During this era, important information was coined by Moore which was later known as Moore’s law
and this law led to the fabrication of more and more transistors on to a single chip. Colloquially
Moore’s law stated that the number of transistors on a single chip doubles each and every eighteen
months. Further developments were LSI (300 to 3000 transistors in a single chip), VLSI (3000 to
30000 transistors in a single chip) and now it the upcoming technology is the ULSI with the
fabrication of millions of transistors in a single chip. Also Moore’s law found a drawback that in
even less than eighteen months the number of transistors in a single chip got doubled.
Also circuits were introduced to do the arithmetic and logic operations. Initially logic operations
such as AND, OR, NOT, NAND, NOR, EX-OR were done by LSI ICs. And circuits for doing
arithmetic operations such as addition subtraction and multiplication were developed which made
the field of signal processing and communication field involving arithmetic operations to glow
more. Half adder was designed to add two one bit numbers and when carry arose, that lead to the
development of full adders which added three one bit numbers and produced. Full adder acts as the
basic block of all adders which are used to perform multi bit additions.
1.3 Problem definition
Signal delay, chip area, and power dissipation are conflicting criteria for designing high-
performance CMOS Full Adder. To ensure all the digital devices be more efficiently working by
designing in a way that the speed is high and power is conserved by scaling down power dissipation.
Slower operation in PTL due to reduced current drive. Due to direct path static power consumption
will increase, it leads to latch up problems and in CMOS technology the numbers of transistors are
required more. Slower operation in PTL due to reduced current drive. Due to direct path static power
consumption will increase, it leads to latch up problems and in CMOS technology the numbers of
transistors are required more.

1.4 Objectives
The Objective of this project is to provide the Full adder is mainly used in VLSI devices like
microprocessor and ASICs for computational purposes. Thus the main aim of this project is to:
1. The adder has been developed using logic level, circuit level and mixed mode implementation.
2. To implement full adder circuit with Reversible logic and using Gate Diffusion input (GDI).
3. Design low power Full adder with reduced number of transistors.
1.5 Methodology
In VLSI digital circuits, power and area reduction is the important parameter which decides the
efficiency of the circuit [1] [4]. Power consumption is the primary factor in high performance
computing application, Image processing applications. The author has said that to compute
irreversible logic, kTln2 joules of heat energy generates per bit information lost [2]. The author
Bennett said that by using reversible logic can eliminate of kTln2 energy dissipation [3].
Another one design technique known as Gate Diffusion Input (GDI) style that replaces CMOS logic
and it was developed for fabrication in SoI and twin-well CMOS process. To ensure all the digital
devices be more efficiently working by designing in way that the speed is high and power is
conserved by scaling down power dissipation.
Slower operation in PTL due to reduced current drive. Due to direct path static power consumption
will increase, it leads to latch up problems and in CMOS technology the numbers of transistors are
required more. Slower operation in PTL due to reduced current drive. Due to direct path static power
consumption will increase, it leads to latch up problems and in CMOS technology the numbers of
transistors are required more. To overcome this problem, the Gate Diffusion Input technique is
proposed reduce number switching activities as well as power consumption. The GDI technique
uses less number of transistors and reduces the area. In this design, we have designed Peres gate
using Gate Input Diffusion using 8 transistors. The proposed new Peres gate is used to design full
adder with power efficient and fault tolerant using reversible logic gates is shown in Figure 1.5.1.
In this design first we have designed 3T XOR gate and 2T AND gate [1]. Peres gate is also coming
under parity preserving reversible gates because it satisfies the following equation (4) and
feedbacks, fan outs are not allowed in this reversible logic.

Figure 1.5.1: Full adder using Peres gate
1.6 Hardware and Software tools used
TANNER TOOL:-
Tanner tool is a Spice Computer Analysis Programmed for Analogue Integrated. Circuits. Tanner
tool consists of the following Engine Machines: S-EDIT. (Schematic Edit), T-EDIT (Simulation
Edit), W-EDIT (Waveforms Edit), LEDIT (Layout Edit) Using these engine tools, spice program
provides facility to the use to design.
The user interface consists of the elements shown below. Unless you explicitly retrieve a setup file,
the position, docking status and other display characteristics are saved with a design and will be
restored when the design is loaded.

Chapter 2
2. Basic Theory
2.1 Adders:
Full Adder is the adder which adds three inputs and produces two outputs as shown in Figure 2.1.1.
The first two inputs are A and B and the third input is an input carry as C-IN. The output carry is
designated as C-OUT and the normal output is designated as S which is SUM as shown in the Table
2.1.1.
A full adder logic is designed in such a manner that can take eight inputs together to create
a byte-wide adder and cascade the carry bit from one adder to the another.
Figure 2.1.1: Block diagram of Full adder
Table 2.1.1: Truth table of Full adder

Evolution of full adder: The basic full adder circuit is designed from its truth table. The logic
diagram of the full adder can be obtained from the logical equations obtained from the truth table.
Figure 2.1.2 shows the logical equations and logic diagram of Full adder consisting OF XOR, AND
& OR gates.
Figure 2.1.2: Block Diagram of Full adder using Logic Gates
2.2 Reversible logic gates:
A reversible logic gate is a memory-less logic element that realizes an injective logical function.
Fredkin gate, Toffoli gate, interaction gate, and switch gate are typical ones. Here, we investigate
basic properties of reversible logic gates and circuits, which are needed in the following chapters.
Reversible logic has various applications in various field like in Nanotechnology, quantum
computing, Low power CMOS, Optical computing and DNA computing, etc. Quantum computation
is One of the most important applications of the reversible logic. Basically reversible circuits do not
lose information & reversible computation is performed only when system comprises of reversible
gates. The reversible logic is design, main purposes are-decrease quantum cost, depth of the circuits
& the number of garbage output.

2.3 Types of Reversible logics:-
There are different types of Reversible logic gates as listed below :-
1.Feynman gate
2.Fredkin gate
3.Peres gate
2.3.1 Feynman gate:-
The Feynman gate is a reversible two-input two-output gate that converts (A, B) to (P , Q ), where
A, B are the inputs and P, Q are the outputs (FG). Its quantum cost is one. The block diagram of
Feynman's gate is shown in figure 2.3.1. The Feynman gate can also be used in reversible logic to
replicate the signal, thereby avoiding the fan-out issue.
Block diagram:
Figure 2.3.1 Block Diagram of Feynman gate
Feynman gate is a 2*2 one through reversible gate as shown in figure 2. The input vectoris I(A, B)
and the output vector is O(P, Q). The outputs are defined by P=A, Q=A XOR B. Quantum cost of a
Feynman gate is 1. Since a fan-out is not allowed in reversible logic, this gate is useful for
duplication of the required outputs as shown in Table 2.3.1.
Table 2.3.1 Truth table of Feynman gate
A B P Q
0 0 0 0
0 1 0 1
1 0 1 1
1 1 1 0

2.3.2 Fredkin gate:-
A Fredkin gate is indeed reversible (3X3) gate that converts (A, B, C) to (P, Q, R), where A,
B, C are the inputs and P, Q, R are the outputs. It is referred to as a 3x3 gate due to the fact that it
may have three inputs & three outputs. The Fredkin gate is shown in Figure 2.3.2.
Figure 2.3.2 Block diagram of Fredkin gate
The input vector is I (A, B, C) and the output vector is O (P, Q, R). The output is defined by P=A,
Q=A′B XOR AC and R=A′C XOR AB. Quantum cost of a Fredkin gate is 5[6] as shown in Table
2.3.2.
Table 2.3.2 Truth table of Fredkin gate
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 0 1
1 1 1 1 1 1
2.3.3 Peres gate:-
A Peres gate is a reversible 3X3 gate that converts (A, B, C) to (P , Q , R ), with A, B, C serving as
the inputs and P, Q, R serving as the outputs as shown in Figure 2.3.3.

Fig 2.3.3 Block diagram Peres gate
Peres gate which is a 3*3 gate having inputs (A, B, C) and outputs P = A; Q = A XOR B; AB XOR
C. It has Quantum cost four as shown in table 2.3.3.
Table 2.3.3 Truth table of Peres gate
A B C P Q R
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
2.4 Gate Diffusion Input:-
With the intensified research in low power, high speed embedded systems such as mobiles, laptops,
etc has led the VLSI technology to scale down to nano regimes, allowing more functionality to be
integrated on a single chip. The wish to improve the performance of logic circuits, once based on
traditional CMOS technology [6], resulted in the development of many logic design techniques
during the last two decades [2, 3]. One form of logic that is popular in low-power digital circuits is
pass-transistor logic (PTL). Formal methods for deriving pass-transistor logic have been presented
for nMOS. They are based on the model, where a set of control signals is applied to the gates of
nMOS transistors.

Another set of data signals are applied to the sources of the n-transistors. The PTL (Pass Transistor
Logic) is most popular for low power digital circuits. Some of the main advantages of PTL over
standard CMOS design.
GDI is a technique which is suitable for design of fast, low power circuits using reduced number of
transistors compared to traditional CMOS design and existing PTL techniques.
The GDI is power and area efficient methodology to design. The structure of GDI cell is shown
below. This structure having 4 terminals G, P, N and D as shown in Figure 2.4.1. G is the common
input between nMOS and pMOS, N and P are diffusion nodes. Here G, P and N acts as inputs and
D acts as an output.
Figure 2.4.1: Gate Diffusion Input (GDI) Cell.
At first glance, the basic cell reminds one of the standard CMOS inverter, but there are some
important differences [1] as mentioned below:
1. The GDI cell contains three inputs: G (common gate input of nMOS and pMOS), P (input to the
source/drain of pMOS), and N (input to the source/drain of nMOS).
2.Bulks of both nMOS and pMOS are connected to N or P (respectively), so it can be arbitrarily biased at
contrast with a CMOS inverter.
The GDI cell structure is different from the existing PTL techniques. It must be remarked that not
all of the functions are possible in standard p-well CMOS process but can be successfully
implemented in twin-well CMOS or silicon on insulator (SOI) technologies.

CHAPTER 3
3. TOOL DESCRIPTION
3.1. DESCRIPTION OF TOOLS USED:
Tanner :
Tanner tool is a Spice Computer Analysis Programmed for Analogue Integrated. Circuits.
Tanner tool consists of the following Engine Machines:
S-EDIT. (Schematic Edit)
T-EDIT (Simulation Edit)
W-EDIT (Waveforms Edit)
LEDIT (Layout Edit)
Using these engine tools, spice program provides facility to the use to design. There are different
types parts on the interface as shown in Figure 3.1.1.
Figure 3.1.1: Parts of the User Interface
Title Bar
The title bar shows the name of the current cell and the view type (symbol, schematic, etc.).
Menu Bar
The menu bar contains the S-Edit menu titles. The menu displayed may vary depending on the view
type that is active. See “Shortcuts for Cell and View Commands” for the various methods S-Edit
provides for executing commands.

Menu List Filtering
Most S-Edit menus and dialogs allow for filtering to speed the process of selecting from a drop-
down list. So, when you enter a character, S-Edit will jump to the first list item that begins with that
character. For example, typing g highlights the first list item beginning with that letter and filters
the display to show only items that begin with g. Typing a u after the g highlights the first list item
beginning with gu, and filters the display to show only items that begin with gu, and so on. The
search procedure is case-insensitive.
Toolbars
You can display or hide individual toolbars using the View > Toolbars command, or by right-
clicking in the toolbar region. Toolbars can be relocated and docked as you like. For added
convenience, S-Edit displays a tool tip when the cursor hovers over an icon.
Standard Toolbar
The Standard toolbar provides buttons for commonly used file and editing commands, as well as
operations specific to S-Edit such as “View Symbol.” There are many options like save, cut, edit,
and View Symbol on the top of interface as shown in figure 3.1.2.
Figure 3.1.2 Standard Toolbar
Draw Toolbar
The Draw toolbar provides tools used to create non-electrical objects, such as rectangles, circles,
and lines, for illustrating and documenting a design as shown in a Figure 3.1.3 in which there are
many options used.

Figure 3.1.3: usage of Tanner tool
Segment Toolbar
The Segment toolbar provides tools with which you limit the degree of angular freedom allowed
when you are drawing wires.
Electrical Toolbar
The Electrical toolbar provides the tools used to create wires, nets, and ports, and to add properties.
SPICE Simulation Toolbar
The SPICE Simulation toolbar lets you extract connectivity, select and probe nets, launch T-Spice
and select evaluated properties.
Locator Toolbar
The Locator toolbar displays the coordinates of the mouse cursor and allows you to quickly change
the units of measurement application-wide.
Mouse Buttons Toolbar
The Mouse Buttons toolbar shows the current functions of the mouse buttons.

Mouse buttons vary in function according to the tool that is active. The Shift, Ctrl and Alt keys can
further change the function. For two-button mice, the middle-button function is accessed by clicking
the left and right buttons at the same time, or by pressing Alt while clicking the left mouse button.
Customizing Toolbars
You can add buttons for existing commands to existing S-Edit toolbars, add entirely new toolbars,
and add new buttons for entirely new commands to either new or existing toolbars.
To customize toolbars, right-click anywhere in the toolbar area and click on Customize in the
Context-sensitive menu. By clicking right side on toolbar we get customization bar as shown in
Figure 3.1.4.
Figure 3.1.4 Customize Toolbar
This opens the Customize dialog, to the Toolbars tab. Note that in this dialog the checkmarks
control only whether or not a toolbar is displayed. The buttons apply only to the toolbar that is
highlighted, and will be applied even if a toolbar is not currently displayed. All toolbars are checked,
so all are displayed. Only Menu Bar is highlighted, so any of the button actions (ex.Reset) will act
only on the Menu Bar.
Reset returns an existing toolbar to the default display settings for aspects such as icon size, tooltips,
etc.– and its original button contents. The New, Rename and Delete functions apply only to custom
toolbars
Adding a Command to a Toolbar
Use the Commands tab to add a button for an existing command to any toolbar. To add a command
to a toolbar, select a category and drag the command out of this dialog box to a toolbar as shown in
Figure 3.1.5.

Figure 3.1.5: Commands Tab
The following steps are to be followed to add command to the tool bar:
1. Right-click in the toolbar area, select Customize and then the Commands tab.
2. Pick the desired command from the Categories list (or use All Commands for a complete list of
available commands), then simply click-and-drag the command from the right column to the
desired toolbar.
3. S-Edit will insert a button displaying the command text, or an icon if one is already defined.
Adding a New Menu
The following steps to be followed to add a new menu using commands:
1. You can also use the Commands tab to add a new menu category to the menu bar.
2. In the Commands tab, scroll down to New Menu at the end of the Categories list.
3. Click-and-drag New Menu from the right column to the Menu bar in the interface.
To add a new menu, use the commands tab to insert a new menu as shown in Figure 3.1.6.
Figure 3.1.6 Adding a New Menu
4. Right-click on the New Menu button you have just placed to open the control menu, where you can
rename it, then check Begin a Group to populate the menu with pull-down commands.

5. Select the new menu button in the interface to open the pull-down group, then click-and-drag from
the Commands tab to add the desired command(s). Make sure to drop the commands within the
group area.
Schematic design of Inverter
Schematic Design:
There are many phases or progressions of a design. A common term you will hear when working
with a Designer is “Schematic Design”. This phase is early in the design process. Schematic Design
establishes the general scope, conceptual ideas, the scale and relationship of the various program
elements. The primary objective of schematic design is to arrive at a clearly defined feasible concept
based on the most promising design solutions.
Opening S-edit platform:
First of all double click on the icon of s-edit on the desktop
or
Go to the start menu >>All Programs >>Tanner EDA >>Tanner Tool v 13.0 >> S-Edit v 13.0 as
shown in Figure 3.1.7.
Figure 3.1.7 Start Tanner
A new window will open and then follow the steps given below:
Go to >>file >> New >> New Design
Select New Design

Figure 3.1.8: New Design
One dialog box will appear as shown in the Figure 3.1.8 then open as follows:
Design Name : Give the name your design as you wish
Create a Folder : Give the path where you want to save the S-Edit Files.
Then Click on ‘OK’
Figure 3.1.9 To Create New Libraries
Now to add libraries in your work click on Add , left on the library window.
Give the path where Libraries are stored . As shown in figure 3.1.9.
C:Documents and SettingsBhowmik.IIIT-3AC288AD0AMy DocumentsTanner EDATanner
Tools v13.0LibrariesAllAll.tanner

Now to create new cell
Go to cell menu >> New view --
Select ‘New view’
The new cell will appear like below as shown in Figure 3.1.10
Design = your design name
Cell = cell no. ( cell no you can change but your design name inv will be same for different cell.
Design name should be changed only when you are going to design another circuit)
View type = schematic
Interface name = “by default”
View name = “by default”
Then press “OK”.
Figure 3.1.10: To create a new cell
Then a cell will be appeared where we can draw the schematic of any circuit. In the black window
you have seen some white bubble arranged in specific order. This is called grid. You can change
grid distance by clicking on black screen and then scroll the mouse. If you want your screen big
enough for design space, then you can close the Find & command window. You can again bring
these window from view menu bar as shown in Figure 3.1.11.

Figure 3.1.11 To Select a New Design
To make any circuit schematic .
for example inverter
a) Go to >>libraries & click on device then all device will be open as shown in Figure 3.1.12.
Figure 3.1.12 To make Circuit Schematic
b) Select any device
e.g. :- NMOS Device, then click on , instance
(then the dailog box instance cell will appear.)

In instance cell
 You can change the values of various device parameters according to your requirements.
 Go to properties >> change the parameter values as your requirement.
 Now before clicking DONE you have to DRAG the selected device into the cell and drop it where
you want it to FIX .
Then click DONE or press ESC.
Similarly you can DRAG & DROP any device into the cell for draw your schematic circuit.
For inverter we need another pmos. Now connect two device with wire and then Go to tool bar and
select wire. Similarly to give input & output port in the circuit , select input port that shown by red
ellipse. Now you can give Port name as you wish in the dailog box. Then click OK and give the
Output Port name.
NOTE : you can rotate the port (short cut key “R”) Now, after completed these steps, you should
give the supply (VDD) & ground (GND). For that Go to liberaries >> MISC >>Select VDD or GND
Now you have to create a source of VDD. For that go to libraries >>spice_element >> and then
select voltage source of type DC . you can give any value in vdd .lets take vdd =5v. By doing all the
above steps you have completed schematic of Inverter
Pre layout simulation
After schematic design you have to check whether your design match with the specification required
or not . That’s why you need to simulate the design which is called Pre layout simulation.
For simulation go to>> tools>> T-spice>> ‘ok’
A “T-spice command Tool “ dialog box will open as shown below.
On the T-spice command you can see in the left hand side
Analysis,
Current source
Files
Initialization,
Output
Settings
Table
Voltage source
Optimization
Lets start doing transient analysis of Inverter.
Step 1 : You have to include TSMC 0.25 μm Technology file .
For that Go to >> T-spice command tool >> Files >> Include >> browse TSMC .25μm files
>> Insert command as shown below:

C:DocumentsandSettingsBhowmik.IIIT-3AC288AD0ADesktopTSMC0.25umMODEL_ 0.25.m
Step2 : Then to give Input
T-spice command tool >> Voltage source >> select type of input you want to give(lets
take bit) >> Insert command
Step 3: Analysis
T-spice command tool >> Analysis >> select type of analysis you want to give(lets take
transient) >> Insert command
step 4: Output
T-spice command tool >> Output >> which output you want to see >> Insert
Command
Now save it .
Then Run by clicking red ellipse shown on left above corner
Output of Pre layout simulation of Inverter
SIMULATION TOOL
The tool used for simulation purpose for the entire research work is Tanner EDA tool version 13.0.
The features and functionality of this tool has been described below:
The design cycle for the development of electronic circuits includes an important pre-fabrication
verification phase. Because of the expense and time pressures associated with the fabrication step,
accurate verification is crucial to efficient design. The role of EDA tool is to help design and verify
a circuit’s operation by numerically solving the differential equations describing the circuit. These
simulation results allow circuit designers to verify and fine-tune designs before submitting them for
fabrication. Tanner EDA tool is a complete circuit design and analysis system that includes:
 Schematic Editor (S-Edit): Schematic editor is a powerful design capture and analysis package that
can generate netlist directly usable in T-Spice simulations.
 T-Spice Circuit Simulator: T-Spice performs fast and accurate simulation of analog and mixed
analog/digital circuits. The simulator includes the latest and best device models available, as well as
coupled line models and support for userdefined device models via tables or C functions. T-Spice
uses an extended version of the SPICE input language that is compatible with all industry standard
SPICE simulation programs. All of SPICE’s device models are incorporated, as well as resistors,
capacitors, inductors, mutual inductors, single and coupled transmission lines, current sources,
voltage sources, controlled sources, and a full complement of the latest advanced semiconductor
device models from Berkeley and Philips Labs.

 Waveform Editor (W-Edit): W-Edit displays T-Spice simulation output waveforms as they are being
generated during simulation. Visualizing the complex numerical data resulting from VLSI circuit
simulation is critical to testing, understanding, and improving those circuits. W-Edit is a waveform
viewer that provides ease of use, power, and speed in a flexible environment designed for graphical
data presentation.
 Layout Editor (L-Edit): Tanner EDA tool includes L-Edit for layout editing,∙ Interactive DRC for
real-time design rule checking during editing, Standard DRC for hierarchical DRC, Standard Extract
for netlist extraction, Standard LVS for layout versus schematic, Node Highlighting for highlighting
all geometry associated with a node and SPR for standard cell place & route.
T-SPICE
To transform your ideas into designs, you must be able to simulate large circuits quickly and with a
high degree of accuracy. That means you need a simulation tool that offers fast run times, integrates
with your other design tools, and is compatible with industry standards. Tanner T-Spice Circuit
Simulator puts you in control of simulation jobs with an easy-to-use graphical interface and a faster,
more intuitive design environment. With key features such as multi-threading support, device state
plotting, real-time waveform viewing and analysis, and a command wizard for simpler SPICE
syntax creation, T-Spice saves you time and money during the simulation phase of your design flow.
T-Spice enables more accurate simulations by supporting the latest transistor models—including
BSIM4 and the Penn State Philips (PSP) model. Given that T-Spice is compatible with a wide range
of design solutions and runs on Windows and Linux platforms, it fits easily and cost effectively into
your current tool flow.
T-Spice incorporates numerous innovations and improvements not found in other SPICE and
SPICE-compatible simulators:
 Speed: T-Spice provides highly optimized code for evaluating device models,∙ formulating the
systems of linear equations, and solving those systems. In addition to the standard direct model
evaluation, T-Spice also provides the option of table-base transistor model evaluation, in which the
results of device model evaluations are stored in tables and reused. Because evaluation of device
models can be computationally expensive, this technique can yield dramatic simulation speed
increases.
 Convergence: T-Spice uses advanced mathematical methods to achieve superior∙numerical stability.
Large circuits and feedback circuits, impossible to analyze with other SPICE products, can be
simulated in T-Spice.
 Accuracy: T-Spice uses very accurate numerical methods and charge conservation to achieve
superior simulation accuracy.
 Macro modeling: T-Spice simulates circuits containing “black box” macro devices. A macro device

can directly use experimental data as its device model. Macro devices can also represent complex
devices, such as logic gates, for which only the overall transfer characteristics, are of interest.
 Input language extensions: The T-Spice input language is an enriched version of the standard
SPICE language. It contains many enhancements, including parameters, algebraic expressions, and
a powerful bit and bus input wave specification syntax.
 External model interface: You can develop custom device models using C or C++.
 Runtime waveform viewing: The W-Edit waveform viewer displays graphical results during
simulation. T-Spice analysis results for voltages, currents, charges, and power can be written to
single or multiple files.
T-Spice also supports foundry extensions, including HSPICE foundry extensions to models.
• Supports PSP, BSIM3.3, BSIM4.6, BSIM SOI 4.0, EKV 2.6, MOS 9, 11, 20, 30, 31, 40,
PSP, RPI a-Si & Poly-Si TFT, VBIC, Modella, and MEXTRAM models.
• Includes two stress effect models, from the Berkeley BSIM4 model and from TSMC
processes, in the BSIM3 model to provide more accuracy in smaller geometry processes.
• Supports gate and body resistance networks in RF modeling.
• Performs non-quasi-static (NQS) modeling.
• Supports comprehensive geometry-based parasitic models for multi-finger devices.
• Models partially depleted, fully depleted, and unified FD-PD SOI devices.
• Models self-heating and RF resistor networks.
• Performs table-based modeling for using measured device data to model a device.
• Includes enhanced diode and temperature equations to improve compatibility with many
foundry model libraries.
Work in a faster, easier design environment
T-Spice helps integrate your design flow from schematic capture through simulation and waveform
viewing. An easy-to-use point-and-click environment gives you complete control over the
simulation process for greater efficiency and productivity.
• Enables easy creation of syntax-correct SPICE through a command wizard.
• Highlights SPICE Syntax through a text editor.
• Provides Fast, Accurate, and Precise options to enable optimal balance of accuracy and
performance.
• Enables you to link from syntax errors to the SPICE deck by double clicking.
• Supports Verilog-A for analog behavioral modeling, allowing designers to prove system
level designs before doing full device level design.
• Provides “.alter” command for easy what-if simulations with netlist changes.

Perform sophisticated analysis
T-Spice uses superior numerical techniques to achieve convergence for circuits that are often
impossible to simulate with other SPICE programs. The types of circuit analysis it performs include:
• DC and AC analysis.
• Transient analysis with Gear or trapezoidal integration.
• Enhanced noise analysis.
• Monte Carlo analysis over unlimited variables and trials with device and lot variations.
• Virtual measurements with functions for timing, error, and statistical analysis including
common measurements such as delay, rise time, frequency, period, pulse width, settling
time, and slew rate.
• Parameter sweeping using linear, log, discrete value, or external file data sweeps.
• 64-bit engine for increased capacity and higher performance.
With T-Spice, you can
• Optimize designs with variables and multiple constraints by applying a Levenberg-
Marquardt non-linear optimizer.
• Perform Safe Operating Area (SOA) checks to create robust designs.
• Use bit and bus logic waveform inputs.
Benefit from flexible licensing
When you purchase a new design tool, licensing options can greatly affect your total cost of
ownership. T-Spice is available in node-locked and networked configurations offering you the most
flexible licensing possible. With a single solution, T-Spice will work whenever and wherever
meeting the design needs of your main workgroup and remote workers. If you offshore design
projects, T-Spice does not have geographic restriction on its licenses, thus, lowering your total cost
of ownership.
SCHEMATIC EDITOR
Schematic Editor (S-Edit) is an easy-to-use PC-based design environment for schematic capture. It
gives you the power you need to handle your most complex full custom IC design capture. S-Edit
is tightly integrated with Tanner EDA’s T-Spice simulation, L-Edit layout, and HiPer verification
tools. S-Edit helps you meet the demands of today’s fast-paced market by optimizing your
productivity and speeding your concepts to silicon. Its efficient design capture process integrates
easily with third-party tools. S-Edit enables you to explore design choices and provides an easy-to-

use view into the consequences of those choices. A faster design cycle gives you more flexibility in
moving to an optimal solution—freeing up more time and resources for process corner validation.
The results are less risk downstream, higher yield, and quicker time to market.
Schematic capture for the most complex full custom IC design
• Bus support speeds the creation of mixed signal designs.
• Advanced array support enables easy creation and editing of memory, imaging, or circuits
with repetitive blocks.
• Rubber band connectivity editing enables faster design modifications.
• S-Edit displays evaluated parameters in real time over the course of the design process.
Parameters with formulas based on other circuit parameters can be displayed or evaluated.
• Auto symbol generation enables you to easily create symbols from schematics, and
synchronize any changes.
• All actions are fully scriptable through the TCL/ Tk command language.
• Recordable scripts enable you to automate tasks or expand the tool for application-specific
needs.
• Replay-able logs permit recovery if there is an unexpected network or hardware failure. • S-
Edit performs net highlighting and keeps the net highlighted as you move through the
hierarchy.
• Cross probe from SPICE net lists and LVS to highlighting nets or devices.
• Schematic ERC enables you to check your design for common errors such as undriven nets,
unconnected pins and multiple output pins connected together. The design checks are fully
configurable, including custom validation scripts.
Tight integration with simulation
• S-Edit is tightly integrated with simulation. You can drive the simulator from within the
schematic capture environment, viewing operating point results directly on the schematic
and performing waveform cross-probing to view node voltages and device terminal currents
or charges.
• S-Edit creates an efficient flow for the iterative loop of design, simulation, analysis, and
tweaking of circuit parameters. The IC designer can focus on the design and not on data
processing—thereby speeding up the design process.
Easy interoperability with third party tools and legacy data
• S-Edit imports schematics via EDIF from third party tools, including Cadence®, Mentor,
Laker and View Draw with automatic conversion of schematics and properties for seamless

integration of legacy data.
• Net lists can be exported in flexible, user-configurable formats, including SPICE and CDL
variants, EDIF, structural Verilog, and structural VHDL.
• Library support in S-Edit maximizes the reuse of IP developed in previous projects, or
imported from third- party vendors.
Powerful and easy-to-use interface
• S-Edit brings to front-end design capture the ease-of-use and design productivity for which
Tanner Tools are known.
• A fully user-programmable design environment allows you to remap hotkeys, create new
toolbars, and customize the view to your preference—all in a streamlined GUI.
• The complete user interface is available in multiple languages. S-Edit currently supports
English, Japanese, Simplified and Traditional Chinese.
• S-Edit provides Unicode support. All user data can be entered in international character sets.
Cost-effective
• S-Edit provides an ideal performance to-cost ratio, allowing you to maximize the number of
designers on a project.
• Since S-Edit is Windows-based, designers can work on cost-effective workstations or
laptops. This means you can take your work with you anywhere—even home—and continue
working to meet time-to-market pressures.
• Available in two configurations—full schematic editor, and schematic viewer.
Easy to manage
• Human-readable technology files and design databases are revision-control system-
compatible.
• CAD managers can control distribution and access rights to the technology or design. The
format allows revision control systems to manage revisions over the course of the design
process.
Benefit from flexible licensing
When you purchase a new design tool, licensing options can greatly affect your total cost of
ownership. S-Edit is available in node-locked and networked configurations offering you the most
flexible licensing possible. With a single solution, S-Edit will work whenever and wherever meeting
the design needs of your main workgroup and remote workers. If you offshore design projects, S-
Edit does not have geographic restriction on its licenses, thus, lowering your total cost of ownership

CHAPTER 4
4.IMPLEMENTATION
A full adder is a digital circuit that performs addition. Full adders are implemented with logic gates
in hardware. A full adder adds three one-bit binary numbers, two operands and a carry bit. The adder
outputs two numbers, a sum and a carry bit. The term is contrasted with a half adder, which adds
two binary digits as shown in Figure 4.1.
Figure 4.1: Schematic of Existing Full Adder
2T and gate consists of one nmos and one pmos transistor. source of nmos is connected to vdd and
drain of pmos connected to ground and drain of nmos and source of pmos are connected to input
and gate terminal of both nmos and pmos are connected to output as shown in Figure 4.2.
Figure 4.2: 2T AND gate using GDI technology
3T Xor gate consists of two pmos transistor and one nmos transistor.one input a will be connected
to gate terminals of pmos and nmos and input b will be connected to source of pmos_1 transistor

and to gate terminal of pmos_2 transistor and source of nmos will be connected to ground as shown
in Figure 4.3.
Figure 4.3: 3T XOR gate using GDI technology
There are 2 AND, 1 OR and 2 EXOR gates required for the configuration of full adder, provided
using half adder as shown in Figure 4.4 otherwise, configuration of full adder would require 3 AND,
2 OR and 2 EXOR.
Figure 4.4 Peres gate using GDI Technology

A full adder circuit is central to most digital circuits that perform addition or subtraction. It Modified
Full adder need to two Peres gate to generate sum and carry as shown in Figure 4.5.
Figure 4.5 Full adder using modified Peres gate

Chapter 5
5.RESULTS AND DISCUSSION
Full Adder is the adder that adds three inputs and produces two outputs. The first two inputs are A
and B and the third input is an input carry as C-IN. The output carry is designated as C-OUT and
the normal output is designated as S which is SUM as shown in Figure 5.1.
Figure 5.1 Output waveform of Existing Full Adder
The AND gate is a basic digital logic gate that implements logical conjunction (∧) from
mathematical logic – AND gate behaves according to the truth table above. A HIGH output (1)
results only if all the inputs to the AND gate are HIGH (1). If not all inputs to the AND gate are
HIGH, LOW output results as shown Figure 5.2.
Figure 5.2 Output waveform of 2T AND gate using GDI

The output of an XOR gate is high (1) only when exactly one of its inputs is high (1). If both of an
XOR gate's inputs are low (0), or if both of its inputs are high (1), then the output of the XOR gate
is low as shown in Figure 5.3.
Figure 5.3 Output waveform of 3T xor gate using GDI
Peres gate which is a 3*3 gate having inputs (A, B, C) and outputs P = A; Q = A XOR B; AB XOR
C. The output results will be like as shown in Figure 5.4.
Figure 5.4 Output waveform of Peres gate using GDI
A full adder logic is designed in such a manner that can take eight inputs together to create a byte-
wide adder and cascade the carry bit from one adder to the another. Full Adder Truth Table: Logical
Expression for SUM: = A' B' C-IN + A' B C-IN' + A B' C-IN' + A B C-IN. = C-IN (A' B' + A B) +
C-IN' (A' B + A B') it will give output as shown in Figure 5.5.

Figure 5.5 Output Waveforms of Full adder using modified Peres gate
Number of transistor required to develop a existing full adder are 46 as shown in Figure 5.6.
Figure 5.6: Area of Existing Full Adder
Average power consumed the circuit while getting outputs are 6.587805e-005
watts as shown in
Figure 5.7.
Figure 5.7: Average power of Existing Full Adder
Delay of the existing full adder is -7.800x10-8
as shown in Figure 5.8.
Figure 5.8: Delay of Existing Full Adder

Number of transistor used in modified Full adder using Peres gate are 16 as shown in Figure 5.9
Figure 5.9: Area of modified Full adder
Average power consumed the circuit while getting outputs are 1.0000000e-12
watts as shown in
figure 5.10.
Figure 5.10: Average power of modified Full Adder
There is a slight less delay in modified full adder while compared to existing full adder as shown in
Figure 5.11.
Figure 5.11: Delay of modified Full adder
Table 5.1: Comparison between existing Full adder and Modified Full adder.
Parameters Existing Full Adder Modified Full Adder
Count of Transistors (Area) 46 16
Average Power 6.5878e-005
watts 1.000000e-12
watts
Delay of Circuit -7.0800e-008
-7.07533e-008

Conclusion and Future scope
CONCLUSION:
The digital devices be more efficiently working by designing in way that the speed is high and power
is conserved by scaling down power dissipation. Slower operation in PTL due to reduced current
drive. Due to direct path static power consumption will increase, it leads to latch up problems and
in CMOS technology the numbers of transistors are required more. Slower operation in PTL due to
reduced current drive. Due to direct path static power consumption will increase, it leads to latch up
problems and in CMOS technology the numbers of transistors are required more. To overcome this
problem, the Gate Diffusion Input technique is proposed reduce number switching activities as well
as power consumption. In this design, Peres Gate is designed using Gate Diffusion Input using 8
transistors. The proposed new Peres Gate is used to design full adder with power efficient and fault
tolerant.
FUTUTRE SCOPE:
The proposed 8T GDI based full adder even though its simplicity and less area make it attractive to
resource-constrained IOT applications but speed is also plays key role in IOT and DSP
applications.so we can even reduce the delay or power consumption by applying Low Power
techniques to the circuits.

vii
REFERENCES
[1] Somashekhar Malipatil, Vikas Maheshwari, and Marepally Bhanu Chandra, “Area
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viii
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ix
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PHOTOGRAPH
KARICHETI
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BAPTLA (D.T),
A.P. 523260
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PLACED
KOPPERLA
YOGESWAR
REDDY
KYOGESWARREDDY1
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AIL.COM
H NO 25-186A,
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DR. HAMSA S
ASSISTANT PROFESSOR
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18BTRECO31 18BTREC090 18BTREC091 18BTREC093

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