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VLSI IEEE 2012 Project @ Hades InfoTech

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Hades InfoTech Pvt Ltd
Hades InfoTech Pvt Ltd

Hades Info Tech offers Real Time IEEE 2009 Projects in Embedded system, Microcontroller like ARM7, ARM9, DSP, VLSI, FPGA, RFID, wireless, ZIGBEE, Robotics, GSM, GPS/GPRS, Bio-Medical, Bio-Metrics, Finger Print, Access Control, MATLAB, Image Processing, Power Electronics

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Hades InfoTech Pvt. Ltd CODE YR VLSI IEEE 2012 – 13 PROJECTS HVL01 A Low Complexity MMSE for OFDM Systems over Frequency-Selective Fading Channels HVL02 Modified Kalman Filters for Channel Estimation in Orthogonal Space-Time Coded Systems HVL03 A Novel All-Digital Multichannel Multimode RF Transmitter Using Delta-Sigma Modulation HVL04 A Low-Power Single-Phase Clock Multiband Flexible Divider IEEE Transaction - 2012 HVL05 High-Speed Low-Power Viterbi Decoder Design for TCM Decoders HVL06 Pipelined Parallel FFT Architectures via Folding Transformation HVL07 Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis HVL08 Low-Complexity Iterative Channel Estimation for Turbo Receivers HVL09 Nonlinear Trellis Codes for Binary-Input Binary-Output Multiple-Access Channels with Single-User Decoding HVL10 FPGA-Based Track Circuit for Railways Using Transmission Encoding HVL11 Accumulator Based 3-Weight Pattern Generation HVL12 Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor HVL13 On Modulo 2^n+1 Adder Design HVL14 Resource-Efficient FPGA Architecture and Implementation of Hough Transform HVL15 Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction IEEE Transaction – 2012 HVL16 Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems HVL17 Testable Path Selection and Grouping for Faster Than At-Speed Testing HVL18 Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity HVL19 A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy HVL20 A Row-Parallel 8 x8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation HVL21 A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers HVL22 Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA HVL23 Sub W Noise Reduction for CIC Hearing Aids HVL24 Perceptually Inspired Noise-Reduction Method for Binaural Hearing Aids No 68/82, L.D.G Road, Little Mount, Saidapet, Chennai-15 Ph: 044-43322196, Mobile: 9840989556, 9952050233 Mail: projects@hades.in, contact@hades.in www.hades.in Page |1

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VLSI IEEE 2012 Project @ Hades InfoTech

  • 1. Hades InfoTech Pvt. Ltd CODE YR VLSI IEEE 2012 – 13 PROJECTS HVL01 A Low Complexity MMSE for OFDM Systems over Frequency-Selective Fading Channels HVL02 Modified Kalman Filters for Channel Estimation in Orthogonal Space-Time Coded Systems HVL03 A Novel All-Digital Multichannel Multimode RF Transmitter Using Delta-Sigma Modulation HVL04 A Low-Power Single-Phase Clock Multiband Flexible Divider IEEE Transaction - 2012 HVL05 High-Speed Low-Power Viterbi Decoder Design for TCM Decoders HVL06 Pipelined Parallel FFT Architectures via Folding Transformation HVL07 Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis HVL08 Low-Complexity Iterative Channel Estimation for Turbo Receivers HVL09 Nonlinear Trellis Codes for Binary-Input Binary-Output Multiple-Access Channels with Single-User Decoding HVL10 FPGA-Based Track Circuit for Railways Using Transmission Encoding HVL11 Accumulator Based 3-Weight Pattern Generation HVL12 Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor HVL13 On Modulo 2^n+1 Adder Design HVL14 Resource-Efficient FPGA Architecture and Implementation of Hough Transform HVL15 Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction IEEE Transaction – 2012 HVL16 Parallel Searching-Based Sphere Detector for MIMO Downlink OFDM Systems HVL17 Testable Path Selection and Grouping for Faster Than At-Speed Testing HVL18 Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity HVL19 A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy HVL20 A Row-Parallel 8 x8 2-D DCT Architecture Using Algebraic Integer-Based Exact Computation HVL21 A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers HVL22 Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA HVL23 Sub W Noise Reduction for CIC Hearing Aids HVL24 Perceptually Inspired Noise-Reduction Method for Binaural Hearing Aids No 68/82, L.D.G Road, Little Mount, Saidapet, Chennai-15 Ph: 044-43322196, Mobile: 9840989556, 9952050233 Mail: projects@hades.in, contact@hades.in www.hades.in Page |1