POA_Unit 5.pptx

Presentation
on
Sub: Processor Organization and Architecture
(POA) (PCCO5020T)
by
Mr. Vishal S. Thakare
B.E. (Computer Engg.)
M.E. (Computer Engg.)
R. C. Patel Institute of Technology, Shirpur
Department of Computer Engineering

Unit 5 – 8051 Microcontroller 5 Hrs.
2
Processor Organization and Architecture

MICROPROCESSORS & MICROCONTROLLERS
 Microprocessor:
 A CPU built into a single VLSI chip is called a
microprocessor.
 It is a general-purpose device and additional external
circuitry are added to make it a microcomputer.
 The microprocessor contains arithmetic and logic unit
(ALU), Instruction decoder and control unit,
Instruction register, Program counter (PC), clock
circuit (internal or external), reset circuit (internal or
external) and registers.
 But the microprocessor has no on chip I/O Ports,
Timers , Memory etc.
 For example, Intel 8085 is an 8-bit microprocessor
and Intel 8086 is a 16-bit microprocessor.
 The block diagram of the Microprocessor is shown in
Fig.
3

4

 MICROCONTROLLER :
 A microcontroller is a highly integrated single chip,
which consists of :
 on chip CPU (Central Processing Unit),
 RAM (Random Access Memory),
 EPROM/PROM/ROM (Erasable Programmable
Read Only Memory),
 I/O (input/output) – serial and parallel,
 timers,
 interrupt controller.
 For example, Intel 8051 is 8-bit microcontroller and
Intel 8096 is 16-bit microcontroller.
 The block diagram of Microcontroller is shown in
Fig.2.
5

 It’s designed to perform application specific tasks that
require a certain degree of control such as a TV
remote, LED display panel, smart watches, vehicles,
traffic light control, temperature control, etc.
 It’s a high-end device with a microprocessor, memory,
and input/output ports all on a single chip.
 It’s the brains of a computer system which contains
enough circuitry to perform specific functions without
external memory.
 Since it lacks external components, the power
consumption is less which makes it ideal for devices
running on batteries.
 Simple speaking, a microcontroller is complete
computer system with less external hardware.
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7

Processor Organization and Architecture 8
Microprocessor Microcontroller
1 Microprocessor is the heart of
Computer system.
Micro Controller is the heart of an
embedded system.
2 It is only a processor, so memory and
I/O components need to be
connected externally
Micro Controller has a processor along
with internal memory and I/O
components.
3 Memory and I/O has to be connected
externally, so the circuit becomes
large.
Memory and I/O are already present,
and the internal circuit is small.
4 You can’t use it in compact systems You can use it in compact systems.
5 Cost of the entire system is high Cost of the entire system is low
6 Due to external components, the total
power consumption is high.
Therefore, it is not ideal for the
devices running on stored power like
batteries.
As external components are low, total
power consumption is less. So it can be
used with devices running on stored
power like batteries.
7 Most of the microprocessors do not
have power saving features.
Most of the microcontrollers offer
power-saving mode.
8 It is mainly used in personal
computers.
It is used mainly in a washing machine,
MP3 players, and embedded systems.

Microprocessor Microcontroller
9 Microprocessor has a smaller number
of registers, so more operations are
memory-based.
Microcontroller has more register.
Hence the programs are easier to write.
10 Microprocessors are based on Von
Neumann model
Micro controllers are based on Harvard
architecture
11
It is a central processing unit on a
single silicon-based integrated chip.
It is a byproduct of the development of
microprocessors with a CPU along with
other peripherals.
12 It has no RAM, ROM, Input-Output
units, timers, and other peripherals
on the chip.
It has a CPU along with RAM, ROM,
and other peripherals embedded on a
single chip.
13 It uses an external bus to interface to
RAM, ROM, and other peripherals.
It uses an internal controlling bus.
14 It’s used for general purpose
applications that allow you to handle
loads of data.
It’s used for application-specific
systems.
15 It’s complex and expensive, with a
large number of instructions to
process.
It’s simple and inexpensive with less
number of instructions to process.

INTEL 8051 MICRCONTROLLER:
 The 8051 microcontroller is a very popular 8-bit
microcontroller introduced by Intel in the year 1981
 The 8051 is based on a Harvard architecture.
 Its 8-bit architecture is optimized for control
applications in embedded systems.
 It is available as a 40-pin DIP chip and works at +5
Volts DC

INTEL 8051 MICRCONTROLLER:
 SALIENT FEATURES: The salient features of 8051
Microcontroller are
 8 bit CPU with registers A and B
 One 16-bit program counter and One 16-bit DPTR ( data
pointer)
 8 bit program status word (PSW)
 8 bit Stack pointer
 4 KB on chip program memory (ROM or EPROM)).
 128 bytes on chip data memory(Internal RAM).
 8-bit data bus
 16-bit address bus
 Two -16 bit timers/counters T0 and T1
 Five Interrupts sources (3 internal and 2external) .
 Four Parallel ports each of 8-bits (PORT0,
PORT1,PORT2,PORT3) with a total of 32 I/O lines.

General Block Diagram of 8051:

 8051 microcontroller is designed by Intel in 1981.
 In the following diagram, the system bus connects all
the support devices to the CPU.
 The system bus consists of an 8-bit data bus, a 16-bit
address bus and bus control signals.
 All other devices like program memory, ports, data
memory, serial interface, interrupt control, timers, and
the CPU are all interfaced together through the system
bus.

1) CPU
 Microcontroller 8051 has a central processing unit which
is also called ALU (Arithmetic Logic Unit) which
performs all arithmetic and logical operation.
2) RAM (Random-access memory)
 Microcontroller 8051 has 128-byte RAM for data storage.
 It is a Volatile type of memory. That means the data is
lost when power to the device is turned off.
 It is used during execution time to store data
temporarily.
 RAM consists of a register bank, stack, and temporary
data storage with some special function registers (SFR’s).

3) ROM (Read Only Memory)
 In 8051, 4KB ROM is available for program storage.
 It is a Non-Volatile type of memory. It means that data is not
lost even in the event of power failure.
 8051 has a 16-bit address. It means it can access 216 (64 KB)
memory locations and we can interface up to 64 KB of
program memory externally in case of large applications.
4) Timers and Counters
 Microcontroller 8051 has two timer pins T0 and T1
 By these timers, we can generate a delay of a particular time in
timer mode
 We can count external pulses or events in counter mode
 Two 16-bit timer registers are available as T0 (TH0 & TL0) and
T1 (TH1 & TL1), e.g. If we want to load T0 then we can load
Higher 8-bit in TH0 & Lower 8-bit in TL0
 TMOD and TCON registers are used to select mode and
control the timer operation

5) Interrupts
 Interrupts are requested by internal or external
peripherals which are masked while unused.
 Interrupt handler routines are called after each
interrupts event occurs.
 These routines are called an Interrupt Service Routine
(ISR) and are located in special memory locations.
 INT0 and INT1 pins used to accept external interrupts.
6) Oscillator
 it is used to provide a clock to the 8051 which decides
the speed.
 We use crystals of frequency varying from 4MHz to 30
MHz.

7) I/O Ports
 8051 has four Input/output port P0, P1, P2, P3
 Each port is 8 bit wide and their SFR (P0, P1, P2, P3) are
bit accessible i.e. we can set or reset individual bit.
8) Serial Communication port
 8051 has two serial communication pins TXD and RXD
used for transmitting and receive data serially via the
SBUF register
 SCON (Serial control) SFR used to control serial
operation

8051 Architectural Block Diagram
A

1. Oscillator and clock generator:
 All operations in a microcontroller are synchronized
by the help of an oscillator clock.
 The oscillator clock generates the clock pulses by
which all internal operations are synchronized.
 A resonant network connected through pins XTAL1
and XTAL2 forms up an oscillator.

2. ALU:
 It is 8 bit unit.
 It performs arithmetic and logical operations like
addition, subtraction, multiplication, division,
increment and decrement, AND, OR and EX-OR etc.
 It manipulates 8 bit and 16 bit data.
 8051 micro controller contains 34 general purpose
registers or working registers.
 Two of them are called math registers A & B and 32 are
bank of registers.

a. Accumulator(A-reg):
 It is 8 bit register and it is bit and byte accessible.
 Result of arithmetic & logic operations performed by ALU is
accumulated by this register.
 Therefore it is called accumulator register.
 It is used to store 8 bit data and to hold one of operand of
ALU units during arithmetical and logical operations.
 Most of the instructions are carried out on accumulator data.
b. B-register:
 It is special 8 bit math register.
 It is bit and byte accessible.
 It is used in conjunction with A register as Input operand for
ALU.
 It is dedicated for Multiplication and Division.
 It is used as general purpose register to store 8 bit data.

c. PSW:
 It is the 8-bit register but only 6-bits are used by 8051
 It is bit and byte accessible.
 It has 4 conditional flags or math flags which sets or
resets according to condition of result.
 It has 3 control flags, by setting or resetting bit required
operation or function can be achieved.
 The format of flag register is as shown below:

MATH FLAG:
1. Carry Flag(CY):
 During addition and subtraction if any carry or borrow is generated then carry
flag is set otherwise carry flag resets.
2. Auxiliary carry flag(AC):
 If during addition and subtraction any carry or borrow is generated from lower
4 bit to higher 4 bit then AC sets else it resets.
3. Overflow flag(OV):
 If in signed arithmetic operations result exceeds more than 7 bit than OV flag
sets else resets.
 It is used in signed arithmetic operations only.
4. Parity flag(P):
 If in result, even no. Of ones "1" are present than it is called even parity and
parity flag sets.
 In result odd no. Of ones "1"are present than it is called odd parity and parity
flag resets.

ii. CONTROL FLAGS:
1. FO:
 It is user defined flag.
 The user defines the function of this flag.
 The user can set ,test n clear this flag through software.
2. RS1 and RS0:
 These flags are used to select bank of register by resetting those
flags which are as shown in table :

3.Program counter(PC):
 8051 has a 16-bit program counter .
 The program counter always points to the address of
the next instruction to be executed.
 After execution of one instruction the program
counter is incremented to point to the address of the
next instruction to be executed.
 It is the contents of the PC that are placed on the
address bus to find and fetch the desired instruction.
 Since the PC is 16-bit width ,8051 can access program
addresses from 0000H to FFFFH, a total of 64kB of
code.

4. Data pointer register(DTPR):
 It is a 16-bit register.
 DPTR, as the name suggests, is used to point to data.
 It is used by a number of commands which allow the
8051 to access external memory.
 It is typically used by the programmer to transfer data
from External RAM.
 When the 8051 accesses external memory it will access
external memory at the address indicated by DPTR.
 This DPTR can also be used as two 8-registers DPH
and DPL.

5. Stack pointer(SP):
 RAM locations from 08H to 1FH can be used as stack.
 Stack is used to store the data temporarily.
 Stack is last in first out (LIFO)
 Stack pointer (SP) is a 8 bit register
 It indicates current RAM address available for stack or
it points the top of stack.
 Initially by default at 07H because first location of
stack is 08H.
 This 8-bit register is incremented before the data is
stored onto the stack using PUSH or CALL
instructions.

 There are four input output ports available P0, P1, P2,
P3.
 Each port is 8 bit wide and has special function
register P0, P1, P2, P3 .
 These registers are bit addressable means each bit can
be set or reset by the Bit instructions (SETB for high,
CLR for low) independently.
 The data at any port which is transmitting or receiving
is in these registers.
 The port 0 can perform dual works.
6. Input / output Ports

 It is also used as Lower order address bus (A0 to A7)
multiplexed with 8 bit data bus. P0.0 to P0.7 is AD0 to
AD7 respectively.
 The address bus and data bus is demultiplexed by the
ALE signal and latch.
 Port 1 is a true I/O port as it doesn’t have any
alternative functions as in P0, but this port can be
configured as general I/O only.
 Port 2 can be used as I/O port as well as higher order
address bus A8 to A15.

 Port 3 also have dual functions it can be worked as I/O as
well as each pin of P3 has specific function.
 P3.0 – RXD – {Serial I / P for Asynchronous
communication Serial O / P for synchronous
communication}.
 P3.1 – TXD – Serial data transmit.
 P3.2 – INT0 – External Interrupt 0.
 P3.3 – INT1 – External Interrupt 1.
 P3.4 – T0 – Clock input for counter 0.
 P3.5 – T1 – Clock input for counter 1.
 P3.6 – WR – Signal for writing to external memory.
 P3.7 – RD – Signal for reading from external memory.
 When external memory is interfaced with 8051 then P0 and
P2 can’t be worked as I/O port they works as address bus
and data bus, otherwise they can be accessed as I/O ports.

 iii. Special function Registers(SFR):
 The 8051 microcontroller has 11 SFR divided in 4
groups:
 A. Timer/Counter register:
 8051 microcontroller has 2-16 bit Timer/counter
registers called Timer-reg-T0(TL0 and TH0) And
Timer/counter Reg-T1(TL1 and TH1).
 Each register is 16 bit register divide into lower and
higher byte register as shown below:
 These register are used to hold initial no. of count.
 All of the 4 register are byte addressable.

 1. Timer control register:
 8051 microcontroller has two 8-bit timer control register
i.e. TMOD and TCON register.
a) TMOD Register:
 it is 8-bit register. Its address is 89H.
 It is byte addressable.
 It used to select mode and control operation of time by
writing control word.
b) TCON register:
 It is 8-bit register. Its address is 88H.
 It is byte addressable.
 Its MSB 4-bit are used to control operation of timer/
counter and LSB 4-bit are used for external interrupt
control.

 B. Serial data register: 8051 micro controller has 2
serial data register viz. SBUF and SCON.
 1. Serial buffer register (SBUF):
 it is 8-bit register. It is byte addressable .
 Its address is 99H.
 It is used to hold data which is to be transferred serially.
 2. Serial control register (SCON):
 it is 8-bit register.
 It is bit/byte addressable.
 The 8-bit loaded into this register controls the operation
of serial communication.

 C. Interrupt register:
 8051 µC has 2 8-bit interrupt register.
 1. Interrupt enable register (IE):
 Its address is A8H.
 it is used to enable and disable function of interrupt.
 2. Interrupt priority register (IP):
 It is 8-bit register.
 Its address is B8H.
 it is used to select low or high level priority of each
individual interrupts.

 D. Power control register (PCON):
 It is byte addressable .
 its bits are used to control mode of power saving circuit,
either idle or power down mode and also one bit is used
to modify baud rate of serial communication.

 Internal RAM OF 8051 :
 This Internal RAM is found on-chip on the 8051 .
 So it is the fastest RAM available, and it is also the most flexible in
terms of reading, writing, and modifying it’s contents.
 Internal RAM is volatile, so when the 8051 is reset this memory is
cleared.
 The 128 bytes of internal RAM is organized as below.
 (i) Four register banks (Bank0, Bank1, Bank2 and Bank3) each of 8-
bytes (total 32 bytes). The default bank register is Bank0. The
remaining Banks are selected with the help of RS0 and RS1 bits of PSW
Register.
 (ii) 16 bytes of bit addressable area and
 (iii) 80 bytes of general purpose area (Scratch pad memory) as shown
in the diagram below. This area is also utilized by the microcontroller as
a storage area for the operating stack.
 The 32 bytes of RAM from address 00 H to 1FH are used as working
registers organized as four banks of eight registers each.
 The registers are named as R0-R7 .Each register can be addressed by its
name or by its RAM address.
 For EX: MOV A,R7 or MOVR7,#05H

 Internal ROM (On –chip ROM):
 The 8051 microcontroller has 4kB of on chip ROM but
it can be extended up to 64kB.
 This ROM is also called program memory or code
memory.
 The CODE segment is accessed using the program
counter (PC) for opcode fetches and by DPTR for data.
 The external ROM is accessed when the EA(active
low) pin is connected to ground or the contents of
program counter exceeds 0FFFH.
 When the Internal ROM address is exceeded the 8051
automatically fetches the code bytes from the external
program memory.

Registers in 8051
 Types of Registers:
 The 8051 microcontroller contains mainly two types of
registers:
 General purpose registers (Byte addressable registers)
 Special function registers (Bit addressable registers)
 The 8051 microcontroller consists of 256 bytes of RAM
memory, which is divided into two ways, such as 128
bytes for general purpose and 128 bytes for special
function registers (SFR) memory.
 The memory which is used for general purpose is
called as RAM memory, and the memory used for SFR
contains all the peripheral related registers like
Accumulator, ‘B’ register, Timers or Counters, and
interrupt related registers.

BASICS OF INTERRUPTS.
 During program execution if peripheral devices needs
service from microcontroller, device will generate interrupt
and gets the service from microcontroller.
 When peripheral device activate the interrupt signal, the
processor branches to a program called interrupt service
routine.
 After executing the interrupt service routine the processor
returns to the main program.
 Steps taken by processor while processing an
interrupt:
 1. It completes the execution of the current instruction.
 2. PSW is pushed to stack.
 3. PC content is pushed to stack.
 4. Interrupt flag is reset.
 5. PC is loaded with ISR address.

 ISR will always ends with RETI instruction. The
execution of RETI instruction results in the following.
 1. POP the current stack top to the PC.
 2. POP the current stack top to PSW.

Classification of interrupts.
 1. External and internal interrupts.
 External interrupts are those initiated by peripheral
devices through the external pins of the
microcontroller.
 Internal interrupts are those activated by the internal
peripherals of the microcontroller like timers, serial
controller etc.
 2. Maskable and non-maskable interrupts.
 The category of interrupts which can be disabled by
the processor using program is called maskable
interrupts.
 Non-maskable interrupts are those category by which
the programmer cannot disable it using program.

Classification of interrupts.
 3. Vectored and non-vectored interrupt.
 Starting address of the ISR is called interrupt vector. In
vectored interrupts the starting address is predefined.
 In non-vectored interrupts, the starting address is
provided by the peripheral as follows.
 Microcontroller receives an interrupt request from
external device.
 Controller sends an acknowledgement (INTA) after
completing the execution of current instruction.
 The peripheral device sends the interrupt vector to the
microcontroller.

8051 INTERRUPT STRUCTURE
 8051 has five interrupts.
 They are maskable and vectored interrupts.
 Out of these five, two are external interrupt and three
are internal interrupts.

 8051 makes use of two registers to deal with interrupts.
1. IE Register
 This is an 8 bit register used for enabling or disabling
the interrupts.
 The structure of IE register is shown below.

 IP Register.
 This is an 8 bit register used for setting the priority of
the interrupts.

TIMERS AND COUNTERS
 The 8051 has two counters/timers which can be used either as
timer to generate a time delay or as counter to count events
happening outside the microcontroller.
 The 8051 has two timers: Timer 0 and Timer 1.
 They can be used either as timers or as counters.
 Both timers are 16 bits wide.
 Since the 8051 has an 8-bit architecture, each 16-bit is accessed as
two separate registers of low byte and high byte.
 First we shall discuss about Timer 0 register.
 Timer0 register is a 16 bits register and accessed as low byte and
high byte.
 The low byte is referred as a TL0 and the high byte is referred as
TH0.
 These registers can be accessed like any other registers.

TIMERS AND COUNTERS
 Timer1 registers is also a 16 bits register and is split
into two bytes, referred to as TL1 and TH1
Timer 0

8051 SERIAL COMMUNICATION
 1. SBUF Register:
 Serial Buffer (SBUF) register is an 8-bit register.
 It has separate SBUF registers for data transmission and for data
reception.
 For a byte of data to be transferred via the TXD line, it must be
placed in SBUF register.
 Similarly, SBUF holds the 8-bit data received by the RXD pin and
read to accept the received data.
 2. SCON register:
 The contents of the Serial Control (SCON) register are shown
below.
 This register contains mode selection bits, serial port interrupt bit
(TI and RI) and also the ninth data bit for transmission and
reception (TB8 and RB8).
 The 8051 supports a full duplex serial port.
 Three special function registers support serial communication.

Frequency of oscillator

 PCON register: Power Control Register

ADDRESSING MODES OF 8051:
 The way in which the data operands are accessed by
different instructions is known as the addressing
modes.
 There are various methods of denoting the data
operands in the instruction.
 The 8051 microcontroller supports mainly 5 addressing
modes. They are
 Immediate addressing mode
 Direct Addressing mode
 Register addressing mode
 Register Indirect addressing mode
 Indexed addressing mode

 1. Immediate addressing.
 In this addressing mode the data is provided as a part of
instruction itself.
 In other words data immediately follows the instruction.
 Eg. MOV A,#30H
 ADD A, #83 # Symbol indicates the data is immediate.

 2. REGISTER ADDRESSING MODE
 In this addressing mode, Data is given by a Register in
the instruction.
 The permitted registers are A, R7 … R0 of each memory
bank.
 Data transfer between two RAM registers is not allowed.
 Example
 MOV A, R0 ; A R0 … If R0 = 25H, then A gets the Value
25H.
 MOV R5, A ; R5 A
 MOV Rx, Ry ; NOT ALLOWED.

 3. DIRECT ADDRESSING MODE
 There are two ways to access the internal memory. Using
direct address and indirect address.
 Using direct addressing mode we can not only address the
internal memory but SFRs also.
 In direct addressing, an 8 bit internal data memory address
is specified as part of the instruction and hence, it can
specify the address only in the range of 00H to FFH.
 In this addressing mode, data is obtained directly from the
memory.
 Eg. MOV A,60h
 ADD A,30h
 MOV 49H, A: Move the contents of the accumulator
into the RAM location 49.

4.Register indirect addressing mode:
 The addressing mode in which a register is used as a
pointer to the data memory block is known as Register
indirect addressing mode.
 In this mode a register is used to hold the actual address of
memory.
 Registers R0 and R1 and DPTR are the only registers that
can be used as data pointers
 Ex :
 MOV A, @ R0: Move the contents of RAM location whose
address is in R0 into A (accumulator)
 MOV @ R1, B: Move the contents of B into RAM location
whose address is held by R1 When R0 and R1 are used as
pointers, they must be preceded by @ sign

 5. Indexed Addressing Mode
 This mode is used to access data from the Code
memory (Internal ROM or External ROM).
 In this addressing mode, address is indirectly specified
as a “SUM” of (A and DPTR) or (A and PC).
 This is very useful because ROM contains permanent
data which is stored in the form of Look Up tables.
 To access a Look Up table, address is given as a SUM of
two registers, where one acts as the base and the other
acts as the index within the table.
 A "C" is present in such instructions, to indicate Code
Memory.

 Example
 MOVC A, @A+DPTR; A = Contents of a ROM
Location pointed by A+DPTR.
 ; If DPTR = 0400H and A = 05H,
 ; Then A gets the contents of ROM Location whose
address is 0405 H.
 MOVC A, @A+PC ; A = Contents of a ROM Location
pointed by A+PC.

Instruction Set of 8051
 The instructions of 8051 can be broadly classified
under the following headings.
 1. Arithmetic Instructions
 2. Data transfer Instructions
 3. Logical Instructions
 4. Program Branching Instructions
 5. Bit Manipulation Instructions / Boolean Variable
Manipulation Instructions

 1. Arithmetic Instructions: Arithmetic instructions
perform several basic arithmetic operations such as
addition, subtraction, division, multiplication etc.
 After execution, the result is stored in the first
operand.

Addition
 In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
 i. ADD A, #45H
 ii. ADDC A, #B4H
ii. Add the contents of A with register Rn with or without carry.
 i. ADD A, R5
 ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without
carry using direct and indirect addressing
 i. ADD A, 51H
 ii. ADDC A, 75H
 iii. ADD A, @R1
 iv. ADDC A, @R0

Subtraction
 In this group, we have instructions to
i. Subtract the contents of A with immediate data with or without
carry.
 i. SUBB A, #45H
 ii. SUBB A, #B4H
ii. Subtract the contents of A with register Rn with or without carry.
 i. SUBB A, R5
 ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or
without carry using direct and indirect addressing
 i. SUBB A, 51H
 ii. SUBB A, 75H
 iii. SUBB A, @R1
 iv. SUBB A, @R0

 Multiplication
 MUL AB.
 This instruction multiplies two 8 bit unsigned
numbers which are stored in A and B register.
 After multiplication the lower byte of the result will be
stored in accumulator and higher byte of result will be
stored in B register.
 Eg. MOV A,#03H ;[A]=03H
 MOV B,#02H ;[B]=02H
 MUL AB ;[A] x [B] = 03 x 05 = 0006
;[A]=06H, [B]=00H

 Division
 DIV AB.
 This instruction divides the 8 bit unsigned number
which is stored in A by the 8 bit unsigned number
which is stored in B register.
 After division the Quotient will be stored in
accumulator and remainder will be stored in B register.
 Eg. MOV A,#05H ;[A]=05H
 MOV B,#02H ;[B]=02H
 DIV AB ; Q = 02 and R = 01
;[A] = 02H, [B]=01H

 DA A (Decimal Adjust After Addition).
 When two BCD numbers are added, the answer is a non-BCD number.
 To get the result in BCD, we use DAA instruction after the addition.
 DAA works as follows.
 If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to
lower nibble.
 If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.
 Eg 1: MOV A,#23H
 MOV R1,#55H
 ADD A,R1 // [A]=78
 DA A // [A]=78 no changes in the accumulator after DAA
 Eg 2: MOV A,#53H
 MOV R1,#58H
 ADD A,R1 // [A]=ABH
 DA A // [A]=11, C=1 . ANSWER IS 111. Accumulator
data is changed after DA A

 Increment: increments the operand by one.
 INC A INC Rn INC DIRECT INC @Ri INC
DPTR
 INC increments the value of source by 1.
 If the initial value of register is FFH, incrementing the value
will cause it to reset to 0.
 In the case of "INC DPTR", two-byte unsigned integer value of
DPTR is incremented.
 If the initial value of DPTR is FFFFh, incrementing the value
will cause it to reset to 0.
 Decrement: decrements the operand by one.
 DEC A DEC Rn DEC DIRECT DEC @Ri
 DEC decrements the value of source by 1.
 If the initial value of is 0, decrementing the value will cause it
to reset to FFh.

 2. Logical Instructions:
 The Logical Instructions are used to perform logical
operations like AND, OR, XOR, NOT, Rotate, Clear
and Swap.
 Logical Instruction are performed on Bytes of data on
a bit-by-bit basis.
 Logical instructions perform logical operations upon
corresponding bits of two registers.
 After execution, the result is stored in the first
operand.

 Logical AND
 ANL destination, source:
 ANL does a bitwise "AND" operation between source
and destination, leaving the resulting value in
destination.
 The value in source is not affected. "AND" instruction
logically AND the bits of source and destination.
 ANL A,#DATA
 ANL A, Rn
 ANL A,DIRECT
 ANL A,@Ri

 Logical OR
 ORL destination, source:
 ORL does a bitwise "OR" operation between source
and destination, leaving the resulting value in
destination.
 The value in source is not affected.
 " OR " instruction logically OR the bits of source and
destination.
 ORL A,#DATA
 ORL A, Rn
 ORL A,DIRECT
 ORL A,@Ri

 Logical Ex-OR
 XRL destination, source
 XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination.
 The value in source is not affected.
 " XRL " instruction logically EX-OR the bits of source and destination.
 XRL A,#DATA
 XRL A,Rn
 XRL A,DIRECT
 XRL A,@Ri
 Logical NOT
 CPL complements operand, leaving the result in operand.
 If operand is a single bit then the state of the bit will be reversed.
 If operand is the Accumulator then all the bits in the Accumulator will
be reversed.
 CPL A, CPL C, CPL bit address
 SWAP A – Swap the upper nibble and lower nibble of A.

 Rotate Instructions
 RR A
 This instruction is rotate right the accumulator.
 Its operation is illustrated below.
 Each bit is shifted one location to the right, with bit 0
going to bit 7.
 RL A
 Rotate left the accumulator. Each bit is shifted one
location to the left, with bit 7 going to bit 0

 RRC A
 Rotate right through the carry.
 Each bit is shifted one location to the right, with bit 0
going into the carry bit in the PSW, while the carry was
at goes into bit 7.
 RLC A
 Rotate left through the carry.
 Each bit is shifted one location to the left, with bit 7
going into the carry bit in the PSW, while the carry
goes into bit 0.

 Data Transfer Instructions:
 Data transfer instructions move the content of one
register to another.
 The register whose content is moved remains
unchanged.
 If they have the suffix “X” (MOVX), the data is
exchanged with external memory

 a. Move the contents of a register Rn to A
 i. MOV A,R2
 ii. MOV A,R7
 b. Move the contents of a register A to Rn
 i. MOV R4,A
 ii. MOV R1,A
 c. Move an immediate 8 bit data to register A or to Rn or to a
memory location(direct or indirect)
 i. MOV A, #45H
 ii. MOV R6, #51H
 iii. MOV 30H, #44H
 iv. MOV @R0, #0E8H
 v. MOV DPTR, #F5A2H
 vi. MOV DPTR, #5467H

 d. Move the contents of a memory location to A or A to a
memory location using direct and indirect addressing
 i. MOV A, 65H
 ii. MOV A, @R0
 iii. MOV 45H, A
 iv. MOV @R1, A
 e. Move the contents of a memory location to Rn or Rn to a
memory location using direct addressing
 i. MOV R3, 65H
 ii. MOV 45H, R2
 f. Move the contents of memory location to another memory
location using direct and indirect addressing
 i. MOV 47H, 65H
 ii. MOV 45H, @R0

 g. Move the contents of an external memory to A or A to an
external memory
 i. MOVX A,@R1
 ii. MOVX @R0,A
 h. Move the contents of program memory to A
 i. MOVC A, @A+PC
 ii. MOVC A, @A+DPTR

 i. Push and Pop instructions
 [SP]=07 //CONTENT OF SP IS 07 (DEFAULT VALUE)
 MOV R6, #25H [R6]=25H //CONTENT OF R6 IS 25H
 MOV R1, #12H [R1]=12H //CONTENT OF R1 IS 12H
 MOV R4, #0F3H [R4]=F3H //CONTENT OF R4 IS F3H
 PUSH R6 [SP]=08 R6=25H
 PUSH R1 [SP]=09 R1=12H
 PUSH R4 [SP]=0A R4=F3H
 POP R6 R6=F3H [SP]=09
 POP R1 R1=12H [SP]=08
 POP R4 R4=25H [SP]=07

 j. Exchange instructions
 The content of source ie., register, direct memory or
indirect memory will be exchanged with the contents of
destination ie., accumulator.
 i. XCH A,R3
 ii. XCH A,@R1
 iii. XCH A,54h
 k. Exchange digit.
 Exchange the lower order nibble of Accumulator (A0-A3)
with lower order nibble of the internal RAM location which
is indirectly addressed by the register.
 i. XCHD A,@R1
 ii. XCHD A,@R0

 Boolean Variable Instructions:
 Boolean or Bit Manipulation Instructions will deal
with bit variables.
 Similar to logic instructions, bit-oriented instructions
perform logic operations.
 The difference is that these are performed upon single
bits.

 1. LOGICAL AND
 a. ANL C,BIT(BIT ADDRESS) ; ‘LOGICALLY AND’ CARRY AND CONTENT OF
BIT ADDRESS, STORE RESULT IN CARRY
 b. ANL C, /BIT; ; ‘LOGICALLY AND’ CARRY AND COMPLEMENT OF
CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
 2. LOGICAL OR
 a. ORL C,BIT(BIT ADDRESS) ; ‘LOGICALLY OR’ CARRY AND CONTENT OF
BIT ADDRESS, STORE RESULT IN CARRY
 b. ORL C, /BIT; ; ‘LOGICALLY OR’ CARRY AND COMPLEMENT OF CONTENT
OF BIT ADDRESS, STORE RESULT IN CARRY
 3. CLR bit
 a. CLR bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE CLEARED.
 b. CLR C ; CONTENT OF CARRY WILL BE CLEARED.
 C. SET C
 D. SET bit
 4. CPL bit
 a. CPL bit ; CONTENT OF BIT ADDRESS SPECIFIED WILL BE
COMPLEMENTED.
 b. CPL C ; CONTENT OF CARRY WILL BE COMPLEMENTED.

 5. Program Branching Instructions: There are two
kinds of branch instructions:
 Unconditional jump instructions: upon their
execution a jump to a new location from where the
program continues execution is executed.
 Conditional jump instructions: Jump to a new
program location is executed only if a specified
condition is met. Otherwise, the program normally
proceeds with the next instruction.

 Unconditional jump instructions:
 The unconditional jump is a jump in which control is transferred
unconditionally to the target location.
 a. LJMP (long jump).
 This is a 3-byte instruction.
 First byte is the op-code and second and third bytes represent the 16-bit
target address which is any memory location from 0000 to FFFFH
 b. AJMP: addr
 This causes unconditional branch to the indicated address, by loading
the 11 bit address to 0 -10 bits of the program counter.
 c. SJMP (short jump).
 This is a 2-byte instruction.
 First byte is the op-code and second byte is the relative target address,
00 to FFH (forward +127 and backward -128 bytes from the current PC
value).
 To calculate the target address of a short jump, the second byte is added
to the PC value which is address of the instruction immediately below
the jump.

 Conditional Jump instructions.
 JNC Jump if CY ＝ 0
 JC Jump if CY ＝ 1
 CJNE reg,#data Jump if byte ≠ #data
 CJNE A,byte Jump if A ≠ byte
 DJNZ Decrement and Jump if A ≠ 0
 JNZ Jump if A ≠ 0
 JZ Jump if A ＝ 0
 All conditional jumps are short jumps.

 Bit level jump instructions:
 Bit level JUMP instructions will check the conditions
of the bit and if condition is true, it jumps to the
address specified in the instruction.
 All the bit jumps are relative jumps.
 JB bit, rel ; jump if the direct bit is set to the
relative address specified.
 JNB bit, rel ; jump if the direct bit is clear to the
relative address specified.
 JBC bit, rel ; jump if the direct bit is set to the
relative address specified and then clear
the bit.

 Call Instructions
 There are two types of CALL instructions
 1. LCALL address(16 bit)
 This is long call instruction which unconditionally calls the
subroutine located at the indicated 16 bit address.
 This is a 3 byte instruction.
 The LCALL instruction works as follows.
 With these the address (0x3254) which was in PC is stored in
stack.
 During execution of LCALL [SP]=[SP]+1; (if SP contains default
value 07, then SP increments and [SP]=08
 [[SP]] = [PC7-0]; (lower byte of PC content ie., 57 will be stored in
memory location 08.
 [SP]=[SP]+1; (SP increments again and [SP]=09)
 [[SP]] = [PC15-8]; (higher byte of PC content ie., 32 will be stored in
memory location 09.
 [PC]= address (16 bit); the new address of subroutine is loaded to
PC. No flags are affected.

 2. ACALL address(11 bit)
 This is absolute call instruction which unconditionally calls
the subroutine located at the indicated 11 bit address.
 This is a 2 byte instruction.
 RET instruction
 RET instruction pops top two contents from the stack and
load it to PC.
 [PC15-8] = [[SP]] ;content of current top of the stack will be
moved to higher byte of PC.
 [SP]=[SP]-1; (SP decrements)
 [PC7-0] = [[SP]] ;content of bottom of the stack will be moved
to lower byte of PC.
 [SP]=[SP]-1; (SP decrements again)

POA_Unit 5.pptx

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