Nowak NVSMW-ICMTD'08

On the Influence of Fin Corner Rounding in 3D Nanocrystal Flash Memories E. Nowak , L. Perniola, G. Ghibaudo*, C. Jahan, P. Scheiblin, G. Reimbold, B. De Salvo, F. Boulanger CEA/LETI-Minatec, 38054 Grenoble, France * IMEP/INPG Grenoble, France [email_address]

Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Nanocrystal FinFlash ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],BOX source Control Gate Fin

Modeling Fowler-Nordheim operation ,[object Object],[object Object],[object Object],[object Object],[object Object],BOX source Control Gate Fin V G

3D TCAD Simulations + ,[object Object],[object Object],+ ATLAS user guide, www.silvaco.com

Model presentation (1/2) ,[object Object],[object Object],[object Object],planar geometry corner geometry

Model presentation (2/2) ,[object Object],[object Object],[object Object]

Present model vs. IEDM’07 model * ,[object Object],[object Object],[object Object],* L. Perniola et al., Tech. Dig of IEDM, pp.943-946, 2007.

[object Object],[object Object],Coupling ratio: planar vs corner regions 1 10 20 30 40 50 0 0.2 0.4 0.6 0.8 1 Curvature radius (nm) Coupling ratio  g planar geometry cylindrical geometry Si/SiO2(5nm)/dots Si/SiO2(13nm)/PolySiN+

Programming window: planar vs. corner regions ,[object Object],[object Object],[object Object], Vt cylin  Vt plan Rc=5.8nm planar No charge stored 10 -7 10 -6 10 -5 10 -4 10 -3 10 -2 0 1 2 3 0 5 10 15 20 -14 -12 -10 -8 -6 -4 -2 0 2 4 (b) (a) Programming windows  Vt [V] Pulse Time t [s] Si HfO2 SiO2 dots Si SiO2 Si Conduction Band Energy [eV] x [nm]

Model vs. 3D TCAD simulation ,[object Object],[object Object],[object Object],Dot A Dot C Dot B Dot D Dot A Dot C Programming windows Δ Vt[V] 10 -7 10 -6 10 -5 10 -4 0 1 2 3 4 Model Simulation Rc=15nm Rc=25nm Pulse Time t [s] 10 -7 10 -6 10 -5 10 -4 -5,0x10 -2 0 Model Simulation Rc=15nm Rc=25nm planar Trapped Charge density Q [C.m -2 ] Pulse Time t [s]

Program/Erase Dynamics of LETI devices ,[object Object],10 -6 10 -4 10 -2 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 10 -6 10 -4 10 -2 Programming windows  Vt [V] Data Model Vg=8V Vg=10V Vg=12V Vg=14V 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 Data Model Vg=-5V Vg=-7V Vg=-9V Vg=-11V Pulse Time t [s] Pulse Time t [s]

Fin Width & Height impact on Δ VT ,[object Object],[2] K. Yanagidaira et al., Jpn. J. Appl. Phys., pp.2608-2611, 2005. H=6 nm 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 Programming windows  Vt [V] H=60 nm 0 20 40 60 80 0 20 40 60 80 Fin Width W [nm] Fin Width W [nm] ref. [2] model planar component cylindrical component

Curvature radius impact on Δ VT ,[object Object],[object Object],Hemispherical R= W/2 6 8 10 12 14 16 18 Curvature radius R [nm] Trigate R  0 10 μ s 100 μ s 10ns  1 s 100ns H=18nm W=36nm Vg=14V 0,0 0,2 0,4 0,6 0,8 1,0 1,2 1,4 1,6 1,8 2,0 2,2 Programming windows  Vt [V]

Conclusion ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Device Fabrication ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Buried oxide Si fin Gate C. Jahan et al., NVSMW-ICMTD ‘08 Poly-Si N + SiO2 Si-ncs HTO Si Poly

The evaluation of access resistance allows to calculate the potential drop along the series of on-pass SOI cells in the NAND string, during write/erase steps V* G-stress V D-inhibit V D-inhibit V G-HIGH V G-HIGH Solution : Write/erase operation for SOI arrays at a cell-by-cell or wordline level Purpose : Source/drain of selected cell must be pinned at ground for efficient write/erase Write/Erase of SOI cells in NAND arrays Problem : Efficient W/E operations for NAND arrays of SOI FD FinFlash.

[object Object],[object Object],[object Object],Access resistance

Scaling limits of Fin Flash devices Thanks to C. Gerardi – STMicroelectronics Y pitch not a concern: L G =30 nm functional devices X pitch is a concern: Enough space to accommodate fin/gate stack/control gate X pitch x = fin + 2d + m = 10nm + 30nm + 5nm = 45 nm F = x/2 = 20-22 nm From ITRS 2007 : 2014 in production

Vt dependence with Radius of curvature ,[object Object],[object Object],[object Object],C.W. Lee et al., Solid State Electronics 51 (2007) pp. 505-510

Nowak NVSMW-ICMTD'08

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