This document provides a summary of Bonnie E. Weir's professional experience and qualifications. She is currently a Principal Engineer at Avago Technologies, with over 30 years of experience in semiconductor device reliability. Some of her key areas of expertise include circuit simulations for power estimation and reliability assurance, electrostatic discharge protection design, and analyzing the reliability of various semiconductor products. She has published extensively in the field and holds several patents related to reliability testing and analysis.

1. Bonnie E. Weir
Avago Technologies, 10A-263C Home Address
1110 American Parkway NE 18 Midland Ave.
Allentown, PA 18109 Bronxville, NY 10708
(610) 712-2042; (610) 712-4081 (Fax) (914) 337-2833
E-mail: bonnie.weir@avagotech.com dnbweir@optonline.net
PROFILE
 Internationally recognized researcher in front-end reliability
 Proficient in circuit simulations for power estimation and reliability assurance
 Experienced designer of on-chip ESD protection
EMPLOYMENT
 Principal Engineer, Foundry Engineering Department, Avago Technologies, Allentown, PA
(May 2014-present)
 Principal Engineer, Reliability Department, LSI Corporation, Allentown, PA (Jan. 2007-May
2014)
 Senior Member of Technical Staff, IC Device Technology Department, Agere Systems,
Allentown, PA (Oct. 2003 – Dec. 2006)
 Member of Technical Staff, AT&T Bell Laboratories, Lucent Technologies and Agere Systems,
Murray Hill, NJ (June, 1988-Sept. 2003)
EDUCATION
1988-1993 Stevens Institute of Technology Hoboken, NJ
Ph.D., Physics and Engineering Physics
Thesis: Fabrication and Analysis of Boron Ordered Delta-doping Layer in Silicon
Advisors: Dean Timothy R. Hart (Stevens) and Dr. L. C. Feldman (Bell Labs)
1985-1988 Swarthmore College Swarthmore, PA
B.A. Physics
Graduated with Honors, Phi Beta Kappa, Sigma Xi
1984-1985 Geneva College Beaver Falls, PA
Charles M. Lee Scholar
General Excellence Award
1980-1984 Canadian Academy Kobe, Japan
Co-Valedictorian, Science Award, National Merit Scholar
MEMBERSHIP AND SERVICE
 Vice-Chair, Dielectrics subgroup, International Reliability Physics Symposium, 1999.
 Member, Dielectrics subgroup, International Reliability Physics Symposium, 2000, 2015, 2016
 Senior Member of Electron Device Society of the IEEE (1995 - present).
 Referee for IEEE Transactions on Electron Devices, IEEE Transactions on Device and Materials
Reliability, Applied Physics Letters, Electron Device Letters, and Physical Review Letters.
 Chair, Presidential Search Committee, Geneva College, Beaver Falls, Pennsylvania, 2015-2016
 Chair, Board of Corporators, Geneva College, Beaver Falls, Pennsylvania, 2008-2013
 Member, Board of Trustees, Geneva College, Beaver Falls, PA, 1995-1999 and 2014-present

2. Bonnie E. Weir
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RESEARCH AND DEVELOPMENT HIGHLIGHTS
Circuit Simulation for Power Estimation (2014-present): Analyzed off-state leakage levels for Avago
and 3rd
-party SRAMs in order to determine expected power dissipation in Normal, Light-sleep and
Deep-sleep modes. Facile with Cadence Spectre and Synopsis HSpice, Hsim and FineSim.
Coordinated test-chip layout forAnalog/Mixed Signal Circuits (2014-present): Led team of physical
designers preparing layouts for 16FinFET shuttle. Compiled final test-chip and submitted to foundry.
Expert user of Cadence Virtuoso and CalibreDRV.
Product-oriented Reliability Analysis (2006-present): Analyzed reliability of Avago, LSI and Agere
Systems products, looking at Time-dependent Dielectric Breakdown, Hot-Carrier Injection, Negative
Bias Temperature Instability, Electromigration and Stress Migration. Analyzed effect of self-heating on
transistor and interconnect reliability. Performed experiments and presented results to customers which
allowed overdrive voltages beyond conventionally acceptable operating voltages. Responsible for
approving all reliability waivers before products can be taped out.
Electrostatic Discharge Protection and Latch-up (2002-2005): Designed testers for ESD protection
systems, executed layout, and performed transmission-line pulse (TLP) testing, creating a database
containing diode, transistor, and power clamp performance for Agere Systems to use in ESD protection
design. Designed complete on-chip ESD protection systems for high-speed applications which met ESD
specifications without sacrificing performance. Showed that projections from DC measurements can
accurately predict the breakdown behavior in the nanoscale regime. Presented at the International
Reliability Physics Symposium and EOS/ESD Symposium, and published in Microelectronics
Reliability.
Scaling Limits of Gate Insulators (1994-2002): Experimentally demonstrated that devices could
continue to function after soft breakdown. Provided evidence for the Anode Hole Injection Model, and
showed that gate oxynitride can be reliably scaled below 2 nm. Our work, considered fundamentally
important for the continued scaling of Silicon IC’s, was documented in 7 invited conference
presentations, 5 journal papers including Nature, and featured prominently in EE Times, Electronics
Weekly, Chemical Engineering News, Business Week, Canberra Times, Sunday Times, and The
Philadelphia Inquirer.
Ordered Delta-Doping of Silicon (1988-1993): Fabricated with Molecular Beam Epitaxy first ordered
delta-doping layer on Si(100). Analyzed using Rutherford Backscattering Spectrometry, grazing-
incidence X-ray diffraction, and Nuclear Reaction Analysis. Presented at the Materials Research
Society, and published as a book chapter as well as in Applied Physics Letters, and Physical Review B.
PATENTS
 “Detecting Breakdown in Dielectric Layers,” G. B. Alers, K. S. Krisch, B. E. Weir, Issued 9/8/1998.
 “Detecting Defects in Integrated Circuits,” G.B. Alers, K.S. Krisch, B.E. Weir, Issued 3/28/2000.
 “Embedded Test Circuitry and a Method for Testing a Semiconductor Device for Breakdown,
Wearout or Failure,” E. Harris, B. E. Weir, Issued 2/19/2008.
 “Hot-Electron Injection Testing Of Transistors On A Wafer” B. E. Weir, Issued 3/1/2011.
 “Semiconductor Device and Process for Reducing Damaging Breakdown in Gate Dielectrics,” T.
Kook, T. Nigam, B. E. Weir, Issued, 1/3/2012
 “Mitigation of Detrimental Breakdown of a High Dielectric Constant Metal-Insulator-Metal
Capacitor in a Capacitor Bank” R. Venkatraman, E. Harris, B. E. Weir, Issued 1/7/2014

3. Bonnie E. Weir
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 “Using Entire Area of Chip in TDDB Checking” K. Banoo, B. E. Weir, Issued 7/8/2014
 “Breaking Up Long Gate-Length Device Used for Low Current Into Small Segments” D. A.
Bell, B. E. Weir, Issued 10/28/2014
 “Checking for High Back-Bias in Long Gate-Length, High Temperature Cases” D. A. Bell,
S. Kuehne, B. E. Weir, Filed 3/15/2013
 “Hot-Carrier Injection Reliability Checks Based on Back Bias Effect on Threshold Voltage”
D. A. Bell, B. E. Weir, Filed 3/15/2013
 “Hot-Carrier Injection Reliability Checks Based on Gate Voltage Dependency” K. Banoo,
D.A. Bell, B.E. Weir, Filed 3/15/2013
 “Hot-Carrier Injection Reliability Checks Based on Bias Temperature Instability – Hot
Carrier Injection Interaction” D.A. Bell, B.E. Weir, Filed 3/15/2013
 “Bias-Temperature Instability Reliability Checks Based on Gate Voltage Threshold for
Recovery” K. Banoo, D. A. Bell, C. Lee, B.E. Weir, Filed 3/15/2013
SELECTED PRESENTATIONS
 M. A. Alam, D. Monroe, B. E. Weir and P. J. Silverman, “Theory of ‘Current-Ratio’ Method for
Oxide Reliability: Proposal and Validation of a New Class of Two-Dimensional Breakdown-Spot
Characterization Techniques,” International Electron Devices Meeting, Dec. 5, 2005
 B. E. Weir, C. C. Leung, P. J. Silverman, M. A. Alam, “Gate Dielectric Breakdown: A Focus on ESD
Protection,” International Reliability Physics Symposium, April 26, 2004.
 B. E. Weir, M. A. Alam, P.J. Silverman, “Low-Voltage Gate Dielectric Reliability,” Electrochemical
Society Meeting, May 14, 2002 (Invited).
 B. E. Weir, M. A. Alam, P. J. Silverman, “Soft Breakdown at all Positions along the NMOSFET,”
Insulating Films on Semiconductors, Udine, Italy, June 19, 2001.
 Panel Discussion: “Is Technology Scaling Limited by Oxide Reliability?” International Reliability
Physics Symposium, April 2000; B. E. Weir, J. McPherson, D. Dumin, C. Hu, E. Vogel, W. Abadeer,
R. Degraeve, S. Hareland.
 B. E. Weir, M. A. Alam, P. J. Silverman, Y. Ma, D. Hwang, “Reliability vs. Performance: What
Limits Gate Oxide Scaling?” SRC Topical Research Conference, Stanford, CA, October, 2000
(Invited).
 B. E. Weir, G. Wilk, M. Alam, P. Silverman, F. Baumann, D. Monroe, A. Ghetti, J. Bude, G. Timp,
A. Hamad, Y. Ma, M. Brown, D. Hwang, T. Sorsch, A. Ghetti, “Ultra-thin Oxide Reliability
Projections & Alternate Dielectrics,” 1st
European Workshop on Ultimate Integration of Silicon,
Grenoble, France, January 2000 (Invited).

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 B. E.Weir, P. Silverman, M. Alam, A. Hamad, F. Baumann, G. Timp, A. Ghetti, Y. Ma, M. Brown,
T. Sorsch, “Gate Oxides in 50nm Devices: Thickness Uniformity Improves Projected Reliability,”
International Electron Devices Meeting, Washington DC, December, 1999 (Invited).
 B. E. Weir, P. J. Silverman, M. A. Alam, J. D. Bude, D. Monroe, N. Zhao, A. Hamad, F. Li, Y. Ma,
M. M. Brown, D. Muller, A. Ghetti, F. Baumann, Y. O. Kim, T. W. Sorsch, G. L. Timp, “Future
ULSI Devices with 1.5-2.5nm Gate Oxides,” First International Workshop on Dielectric Thin Films
for Future ULSI Devices, Tokyo, Japan, October 1999 (Invited).
 B. E. Weir, P. J. Silverman, G. B. Alers, D. Monroe, M. A. Alam, T. W. Sorsch, M. L. Green, G. L.
Timp, Y. Ma, M. Frei, F. Baumann, C. T. Liu, J. D. Bude, and K. S. Krisch, “Soft Breakdown in
Ultra-thin Dielectrics,” Materials Research Society, San Francisco, CA, April 6, 1999 (Invited).
 B. E. Weir, P. J. Silverman, K. S. Krisch, D. Monroe, M. A. Alam, G. B.Alers, G. L. Timp, T. W.
Sorsch, M. L. Green, F. Baumann, Y. Ma, B. J. Sapjeta, T. Boone, J. Rosamilia, D. Hwang, “Soft
Breakdown in Thin Oxides,” Joint SRC/Sematec Reliability Topical Conference, Nashville, TN, Oct.
22, 1997 (Invited).
 B. E. Weir, H. Nussbaumer, K. S. Krisch, D. Monroe, M-T. Tang, K. W. Evans-Lutterodt, M. L.
Green, D. Brasen, L. Manchanda, “Barrier Height Measurements in O2 and N2O Gate Dielectrics,”
Semiconductor Interface Specialists Conference, December 1995.
 B. E. Weir, L. C. Feldman, M. Needels, M. S. Hybertsen, M. Schluter, R. L. Headrick, Q. Shen, T. R.
Hart, “Epitaxially Grown Ordered Boron Delta-Doping Layer,” Materials Research Society, San
Francisco, CA, April 1993.
 B. E. Weir, R. L. Headrick, Q. Shen, L. C. Feldman, M. Needels, M. S. Hybertsen, M. Schluter,
“Structure of a Si(100)B-(2x1)/Si Buried Ordered Doping Layer” Physics and Chemistry of
Semiconductor Interfaces Conference, Death Valley, CA, January 1991.
 B. E. Weir, D. Brasen, M. L. Green, J. C. Bean, R. L. Headrick, L. C. Feldman, “Mechanically and
Thermally Stable Si-Ge RTCVD Layers Grown at 900C” 37th
Annual American Vacuum Society
Symposium and Topical Conference, Toronto, Canada, October 1990.
SELECTED PUBLICATIONS
 D. Varghese, B. Weir, and M. A. Alam, “A generalized, IB-independent, physical HCI lifetime projection
methodology based on universality of hot-carrier degradation”, to appear in International Reliability
Physics Symposium, April, 2010.
 B. E. Weir, C. C. Leung, P. J. Silverman, M. A. Alam, “Gate Dielectric Breakdown in the Time-scale
of ESD Events” Microelectronics Reliability 45 p. 427 (2005).
 B. E. Weir, M. Alam, P. Silverman, F. Baumann, D. Monroe, A. Ghetti, J. Bude, G. Timp, A. Hamad,
Y. Ma, M. Brown, D. Hwang, T. Sorsch, A. Ghetti, G. Wilk, “Ultra-thin Oxide Reliability
Projections” Solid State Electronics 46 p. 321 (2002).
 B. E. Weir, M. A. Alam, J. D. Bude, P. J. Silverman, A. Ghetti, F. Baumann, P. Diodato, D. Monroe,
T. Sorsch, G. Timp, Y. Ma, M. M. Brown, A. Hamad, D. Hwang, P. Mason, “Gate Oxide Reliability
Projection to the Sub-2nm Regime” Semiconductor Science & Technology 15, p. 455 (2000).

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 B. E. Weir, P. J. Silverman, D. Monroe, K. S. Krisch, M. Alam, G. Alers, T. W. Sorsch, G. L. Timp,
F. Baumann, C. T. Liu, Y. Ma, D. Hwang, “Ultra-Thin Gate Dielectrics: They Break Down But Do
They Fail?” IEDM Tech. Digest p. 73 (1997).
 B. E. Weir, D. J. Eaglesham, L. C. Feldman, H. S. Luftman, R. L. Headrick, “Electron Microscopy of
the Ordered Boron 2x1 Structure Buried in Crystalline Silicon” Appl. Surf. Sci. 84, p. 413 (1995).
 B. E. Weir, L. C. Feldman, D. Monroe, H. –J. Gossmann, R. L. Headrick, T. R. Hart, “Electrical
Characterization of an Ultra-High Concentration B Delta-Doping Layer” Appl. Phys. Lett. 65, p. 737
(1994).
 B. E. Weir, R. L. Headrick, Q. Shen, L. C. Feldman, T. R. Hart, M. Needels, M. S. Hybertsen, M.
Schluter, “Boron-Silicon Compound Delta Layer – A New Approach to Doping” Phys. Rev. B 46, p.
12861 (1992).
 B. E. Weir, B. S. Freer, R. L. Headrick, D. J. Eaglesham, G. H. Gilmer, J. Bevk, L. C. Feldman, “Low
Temperature Homoepitaxy on Si(111)” Appl. Phys. Lett. 59, p. 204 (1991).
 M. A. Alam, D. Monroe, B. E. Weir, P. J. Silverman, “Theory of ‘Current-Ratio’ Method For Oxide
Reliability: Proposal and Validation of a New Class Two-Dimensional Breakdown-Spot
Characterization Techniques” IEDM Tech. Digest to be published (2005).
 R. A. Ashton, B. E. Weir, G. Weiss, T. Meuse, “Voltages Before and After HBM Stress and Their
Effect on Dynamically Triggered Power Supply Clamps” EOS/ESD Symposium Proceedings p.153
(Sep. 2004).
 M. A. Alam, R. K. Smith, B. E. Weir, and P. J. Silverman, “Uncorrelated Breakdown of Silicon
Integrated Circuits,” Nature 6914 p. 378 (2002)
 M. A. Alam, R. K. Smith, B. E. Weir, P. J. Silverman, “Statistically Independent Soft Breakdowns
Redefine Oxide Reliability Specifications” IEDM Tech. Digest p. 151 (2002).
 M. Alam, B. Weir, P. Silverman, “A Future of Function or Failure?” Circuits and Devices Magazine
p. 42 (March 2002).
 M. A. Alam, B. E. Weir, P. J. Silverman, “A Study of Soft and Hard Breakdown: Parts I & II” IEEE
Transactions on Electron Devices 49 p. 232 (2002).
 M. Alam, B. Weir, P. Silverman, Y. Ma, D. Hwang, “The Statistical Distribution of Percolation
Resistance as a Probe into the Mechanics of Ultra-Thin Oxide Breakdown” IEDM Tech. Digest p. 529
(2000).
 M. A. Alam, B. Weir, P. Silverman, J. Bude, A. Ghetti, Y. Ma, M.M. Brown, D. Hwang, A. Hamad,
“Physics and Prospects of Sub-2nm Oxides” The Physics and Chemistry of SiO2 and the Si-SiO2
Interface – 4, H. Z. Massoud, I. J. R. Baumvol, M. Hirose, and E. H. Poindexter, eds. Pennington, NJ:
The Electrochemical Society, 2000, p. 365.
 M. Alam, J. Bude, B. Weir, P. Silverman, D. Monroe, K. P. Cheung, “An Anode Hole Injection
Percolation Model for Oxide Breakdown–The Doom’s Day Scenario Revisited” IEDM Tech. Digest
p. 715 (1999).

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 M. Alam, B. Weir, J. Bude, P. Silverman, D. Monroe, “Explanation of Soft & Hard Breakdown & its
Consequences for Area-Scaling” IEDM Tech. Digest p. 449 (1999).
 J. D. Bude, B. E. Weir, P. J. Silverman, “Explanation of Stress-Induced Damage in Thin Oxides”
IEDM Tech. Digest p. 179 (1998).
 G. Timp, K. K. Bourdelle, J. E. Bower, F. H. Baumann, T. Boone, R. Cirelli, K. Evans-Lutterodt, J.
Garno, A. Ghetti, H. Gossmann, M. Green, D. Jacobson, Y. Kim, R. Kleiman, F. Klemens, A.
Kornblit, C. Lochstampfor, W. Mansfield, S. Moccio, D. A. Muller, L. E. Ocola, M. L. O’Malley, J.
Rosamilia, J. Sapjeta, P. Silverman, T. Sorsch, D. M. Tennant, W. Timp, B. E. Weir, “Progress
Toward 10nm CMOS Devices” IEDM Tech. Digest p. 615 (1998).
 G. B. Alers, B. E. Weir, M. A. Alam, G. L. Timp, T. W. Sorsch, “Trap Assisted Tunneling as a
Mechanism of Degradation & Noise in 2-5nm Oxides” Proceedings of 36th
Int’l Reliability Physics
Symposium, p. 76 (1998).
 M. L. Green, T. W. Sorsch, G. Timp, H. C. Lu, J. Sapjeta, P. J. Silverman, B. E. Weir, “Rapid
Thermal Growth of Ultrathin ( 2.0 nm) Oxides & Oxynitrides for ULSI Using NO-O2 Gas
Mixtures” Proceedings of the 6th
Int’l Conf. on Adv. Thermal Proc. of Semicond. p. 72, Kyoto, Japan
(1998).
 T. W. Sorsch, W. Timp, F. H. Baumann, K. H. A. Bogart, T. Boone, V. Donnelly, M. L. Green, K.
Evans-Lutterodt, C. Y. Kim, J. Rosamilia, B. J. Sapjeta, P. J. Silverman, B. E. Weir, G. L. Timp,
“Ultra-thin, 1.03-3.0 nm, Gate Oxides for High Performance Sub-100nm Technology” VLSI
Technology Symposium Proceedings, p. 222, Honolulu, Hawaii (1998).
 F.W. Sexton, D.M. Fleetwood, M.R. Shaneyfelt, P.E. Dodd, G.L. Hash, L.P. Schanwald, R.A.
Loemker, K.S. Krisch, M.L. Green, B.E. Weir, P.J. Silverman, “Precursor Ion Damage and Angular
Dependence of Single Event Gate Rupture in Thin Oxides” IEEE Trans. on Nucl. Sci. 45, 2509
(1998).
 G. Timp, A. Agarwal, F. H. Baumann, T. Boone, M. Buonanno, R. Cirelli, V. Donnelly, M. Foad, D.
Grant, M. Green, H. Gossmann, S. Hillenius, J. Jackson, D. Jacobson, R. Kleiman, A. Kornblit, F.
Klemens, J. T-C. Lee, W. Mansfield, S. Moccio, A. Murrell, M. O’Malley, J. Rosamilia, J. Sapjeta, P.
Silverman, T. Sorsch, W. W. Tai, D. Tennant, H. Vuong, B. Weir, “Low Leakage Ultra-thin Gate
Oxides for Extremely High Performance sub-100nm nMOSFETs” IEDM Tech. Digest p. 930 (1997).
 J. Sapjeta, T. Boone, J. M. Rosamilia, P. J. Silverman, T. W. Sorsch, G. Timp, B. E. Weir,
“Minimization of Interfacial Microroughness for 13-60A Ultrathin Gate Oxides” Mat. Res. Soc.
Symp. Proc. 477, 203 (1997).
 G.B.Alers, A.S. Oates, D. Monroe, K.S. Krisch, and B.E. Weir, “Effect of Electronic Corrections on
the Thickness Dependence of Thin Oxide Reliability” Appl. Phys. Lett. 71, 2478 (1997).
 G. B. Alers, D. Monroe, K. S. Krisch, B. E. Weir, A. M. Chang, “Tunneling Current Noise in Thin
Gate Oxides” Appl. Phys. Lett., 69, 2885 (1996).
 R. L Headrick, L. C. Feldman, B. E. Weir, Book Chapter: “Ordered Delta-doping” Delta-Doping of
Semiconductors, ed. E. F. Schubert, Cambridge University Press (1995).

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 E. A. Fitzgerald, Y.-H. Xie, D. Monroe, P. J. Silverman, J.–M. Kuo, A. R. Kortan, F. A. Thiel, B. E.
Weir, L. C. Feldman, “Relaxed GexSi1-x Structures for III-V Integration with Si and High Mobility
Two-Dimensional Electron Gases in Si” J. Vac. Sci. Tech. B. 10, 1807, (1992).
 A. Katz, S. N. G. Chu, B. E. Weir, C. R. Abernathy, S. J. Pearton, W. S. Hobson, “Rapid Isothermal
Processing of Pt/Ti contacts to p-Type III-V Binary and Related Ternary Materials” IEEE Trans. on
Elec. Dev. 39, 184 (1992).
 R. L. Headrick, B. E. Weir, A. F. J. Levi, B. S. Freer, J. Bevk, L. C. Feldman, “Ordered Monolayer
Structures of Boron in Si(111) and Si(100)” Journal of Vacuum Science and Technology A9, 2269
(1991).
 M. L. Green, B. E. Weir, D. Brasen, Y.-F. Hsieh, G. Higashi, A. Feygenson, L. C. Feldman, R. L.
Headrick, “Mechanically and Thermally Stable Si-Ge Films and Heterojunction Bipolar Transistors
Grown by Rapid Thermal Chemical Vapor Deposition at 900C” J. Appl. Phys. 69, 745 (1991).
 Y.–J. Mii, Y. H. Xie, E. A. Fitzgerald, D. Monroe, F. A. Thiel, B. E. Weir, L. C. Feldman,
“Extremely High Electron Mobility in Si/GexSi1-x Structures Grown by Molecular Beam Epitaxy”
Appl. Phys. Lett. 59, 1611 (1991).
 E. A. Fitzgerald, Y. H. Xie, M. L. Green, D. Brasen, A. R. Kortan, J. Michel, Y.–J. Mii, B. E. Weir,
“Totally relaxed GexSi1–x layers with low threading dislocation densities grown on Si substrates”
Appl. Phys. Lett. 59, 811 (1991).
 J. Benton, J. Michel, L. C. Kimerling, B. E. Weir, R. A. Gottscho, “Carbon Reactions in Reactive Ion
Etched Silicon” J. Elec. Mats. 20, 643 (1991).
 L.–W. Tu, E. F. Schubert, H. M. O’Bryan, Y. H. Wang, B. E. Weir, G. Zydzik, A. Y. Cho,
“Transparent Conductive Metal-Oxide Contacts in Vertical-Injection Top-Emitting Quantum Well
Lasers” Appl. Phys. Lett. 58, 790 (1991).
 G. Hasnain, K. Tai, L. Yang, R. J. Fischer, J. D. Wynn, B. E. Weir, N. K. Dutta, A. Y. Cho,
“Performance of Gain-Guided Surface Emitting Lasers with Semiconductor Distributed Bragg
Reflectors” IEEE J. of Quantum Electronics, 27, 1377 (1991).
 R. L. Headrick, B. E. Weir, J. Bevk, B. S. Freer, D. J. Eaglesham, L. C. Feldman, “Influence of
Surface Reconstruction on the Orientation of Homoepitaxial Silicon Films” Phys. Rev. Lett. 65, 1128
(1990).
 R. L. Headrick, B. E. Weir, A. F. J. Levi, D. J. Eaglesham, L. C. Feldman, “The Si(100)-(2x1) Boron
Reconstruction: Self-Limiting Monolayer Doping” Appl. Phys. Lett. 57, 2779 (1990).
 R. A. Modavis, D. G. Hall, J. Bevk, B. S. Freer, L. C. Feldman, B. E. Weir, “Isoelectronic Bound
Exciton Emission from Si-Rich Silicon-Germanium Alloys” Appl. Phys. Lett. 57, 954 (1990).
 E. A. Fitzgerald, Y. H. Xie, D. Brasen, M. L. Green, J. Michel, P. E. Freeland, B. E. Weir,
“Elimination of Dislocations in Heteroepitaxial MBE and RTCVD GexSi1-x Grown on Patterned Si
Substrates” J. Electr. Mats. 19, 949 (1990).

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 A. Katz, B. E. Weir, S.N.G. Chu, P. M. Thomas, M. Soler, T. Boone, W. Dautremont-Smith,
“Pt/Ti/n-InP Nonalloyed Ohmic Contact Formed by Rapid Thermal Processing” J. Appl. Phys. 67,
3872, (1990).
 A. Katz, B. E. Weir, D. Maher, P. M. Thomas, M. Soler, W. C. Dautremont-Smith, R. F. Karlicek, Jr.,
J. D. Wynn, L. C. Kimerling, “Highly Stable W/p-In0.53Ga0.47As Ohmic Contacts Formed by Rapid
Thermal Processing” Appl. Phys. Lett. 55, 2220, (1989)