4. What is Pipelining
Pipelining is the process of accumulating instruction from the processor through a
pipeline. It allows storing and executing instructions in an orderly process. It is also
known as pipeline processing.
Pipelining is a technique where multiple instructions are overlapped during
execution. Pipeline is divided into stages and these stages are connected with one
another to form a pipe like structure. Instructions enter from one end and exit from
another end.
5. In pipeline system, each segment consists of an input register followed by a
combinational circuit. The register is used to hold data and combinational circuit
performs operations on it. The output of combinational circuit is applied to the input
register of the next segment.
6. Types of Pipeline
It is divided into 2 categories:
Arithmetic Pipeline
Instruction Pipeline
7. Arithmetic Pipeline
Arithmetic pipelines are usually found in most of the computers. They are used for
floating point operations, multiplication of fixed point numbers etc. For example:
The input to the Floating Point Adder pipeline is:
Here A and B are mantissas (significant digit of floating point numbers),
while a and b are exponents.
X = A*2^a
Y = B*2^b
8. Instruction Pipeline
In this a stream of instructions can be executed by
overlapping fetch, decode and execute phases of an instruction cycle. This type of
technique is used to increase the throughput of the computer system.
An instruction pipeline reads instruction from the memory while previous
instructions are being executed in other segments of the pipeline. Thus we can
execute multiple instructions simultaneously. The pipeline will be more efficient if
the instruction cycle is divided into segments of equal duration.
9. Introduction:
Very long instruction word (VLIW) describes a computer processing architecture in
which a language compiler or pre-processor breaks program instruction down into
basic operations that can be performed by the processor in parallel (that is, at the
same time).
10. Who invented VLIW
The concept of VLIW architecture, and the term VLIW, were invented by Josh
Fisher in his research group at Yale University in the early 1980s.
This technology is used by first Intel i860.
11. Features :
The processors in this architecture have multiple functional units, fetch from the
Instruction cache that have the Very Long Instruction Word.
Multiple independent operations are grouped together in a single VLIW Instruction.
They are initialized in the same clock cycle.
Each operation is assigned an independent functional unit.
All the functional units share a common register file.
13. Advantages :
Reduces hardware complexity.
Reduces power consumption because of reduction of hardware complexity.
Since compiler takes care of data dependency check, decoding, instruction issues, it
becomes a lot simpler.
Increases potential clock rate.
Functional units are positioned corresponding to the instruction pocket by
compiler.
14. Disadvantages :
Complex compilers are required which are hard to design.
Increased program code size.
Larger memory bandwidth and register-file bandwidth.
Unscheduled events, for example a cache miss could lead to a stall which will stall
the entire processor.
In case of un-filled opcodes in a VLIW, there is waste of memory space and
instruction bandwidth.
15. Software Pipelining:
Software pipelining (also known as loop pipelining and loop folding) is a technique
that overlaps loop iterations (i.e., subsequent iterations start before previous
finished).
This technique is suitable to increase performance but may also increase register
pressure.
One of the most used software pipelining techniques is the iterative modulo
scheduling.
16.
17. Software Pipelining:
An important parameter used in software pipelining is the Initiation Interval , which
identifies the number of cycles between the start of successive iterations.
The ultimate goal of software pipelining to maximize performance is to achieve an
II of one clock cycle, which means that the kernel is executed at one iteration per
cycle.
18. Local Scheduling:
Pipeline Scheduler is a total software solution for pipeline scheduling.
Pipeline Scheduler is a comprehensive, fully featured system designed to manage
the commercial and operational data that are necessary to operate a pipeline
efficiently.
It allows the user to rapidly collect shipping requests and create a working
schedule which can be managed through its active period.
19. Pipeline Scheduler is the premier solution
for:
Managing nominations
Cycling plan break down of transport batches
Scheduling transportation using a full suite of capabilities
Predicting bottlenecks and constraints across the entire pipeline network
Determining tank positions and possible violations
Minimizing product transmix and quality degradation
Producing reports such as batch and operational schedules
20. When would a pipeline schedule be used:
Pipeline schedules can be used to run a pipeline at specific intervals, for example
every month on the 22nd for a certain branch.
21. Benefits of scheduled pipelines in
continuous integration:
Scheduling is an integral part of software development practices. Tools for
scheduling jobs help development teams save time by scheduling recurring tasks
— like modifying a database or sending out periodic emails — for execution at
specified times.
Continuous integration and continuous delivery (CI/CD) is another important tool
that allows developers to automate recurring processes like building, testing,
deploying, and releasing software.
22. There are three categories of jobs that most
often benefit from a scheduled pipeline:
Deploying artifacts
Testing
Maintenance Let’s further explore these three types of scheduled CI/CD work.
23. Use cases for scheduled pipelines:
Security checks outside the normal commit-push cycle
Refreshing and resetting resources
Running regular QA tests on builds
Data cleanup
Load testing
Sending reports and notifications
24. Loop Unrolling:
Loop unrolling is a technique for attempting to minimize the cost of loop overhead,
such as branching on the termination condition and updating counter variables.
This occurs by manually adding the necessary code for the loop to occur multiple
times within the loop body and then updating the conditions and counters
accordingly.
The potential for performance improvement comes from the reduced loop
overhead, since less iterations are required to perform the same work, and also,
depending on the code, the possibility for better instruction pipelining.
25. Loop transformations:
Loops are important program structures—although they are compactly described
in the source code, they often use a large fraction of the computation time. Many
techniques have been designed to optimize loops.
A simple but useful transformation is known as loop unrolling, illustrated in the
next example. Loop unrolling is important because it helps expose parallelism that
can be used by later stages of the compiler.
26. Example:
Here is a simple C loop:
for (i = 0; i < N; i++) {
a[i]=b[i]*c[i];
}
This loop is executed a fixed number of times, namely, N.
If we let N = 4, then we can substitute this straight-line code for the loop:
a[0] = b[0]*c[0];
a[1] = b[1]*c[1];
a[2] = b[2]*c[2];
a[3] = b[3]*c[3];
27. Loop fusion combines two or more loops into a single loop. For this
transformation to be legal, two conditions must be satisfied. First, the loops must
iterate over the same values. Second, the loop bodies must not have dependencies
that would be violated if they are executed together.
Loop distribution is the opposite of loop fusion, that is, decomposing a single
loop into multiple loops.
28. MCQS:
1). Pipelining is a ------------technique?
a) Serial operation b) Parallel operation
c) Scalar operation d) Superscalar operation
2). Each stage of instruction should execute in ---------cycles?
a)1 b) 2
c) 3 d) 4
3). Parallelism can be achieved by-----------technique.
a) Hardware b) Compiler
c) Software d) All of the above
4). In a pipelined processor, the processing units for integers and floating point is-------?
a) Same unit b) Separate unit
c) No unit d) Within each other
5). ARM processors are available in the form of -------- pipelining?
a) 3 stage b) 5 stage
c) Both a and b d) None of the above
6). The stages of 3 stage pipelining are----?
a) Fetch, Decode, Execute b) Decode, Fetch, Execute
c) Execute, Fetch, Decode d) Address generation, Fetch, Execute.
29. Questions:
1. What is Pipelining?
2. Who invented VLIW?
3. When would a pipeline schedule be used?
4. Write Use cases for scheduled pipelines.
5. What is loop unrolling?
