IMAX3: Amazing Dataflow-Centric CGRA and its Applications I present this slide to all hungry engineers who are tired of CPU, GPU, FPGA, tensor core, AI core, who want some challenging one with no black box inside, and who want to improve by themselves.

1. CPU GPU
Ultimate CGRA w/ high-speed compiler
CGRA for Energy-efficient Cryptography
Beyond-Neuromorphic Systems
Non-Deterministic Computing
1
ナレータ VOICEVOX:もち子(cv 明日葉よもぎ)
はらぺこエンジニアに贈るCGRAの世界2022
（2. 画像フィルタ初級編）
スパコンからIoTまで 省エネ社会に
AI+BCだけじゃない超効率計算手法

2. /* SCREEN=WD*HT */
for (row=0; row<HT; row++) {
for (col=0; col<WD; col++) {
pix = in[row*WD+col];
r = t[ pix>>24 ];
g = t[256+((pix>>16)&255)];
b = t[512+((pix>> 8)&255)];
out[row*WD+col]=r<<24 | g<<16 | b<<8;
} }
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簡単な tone_curveをC言語で書く
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Store ←
Color map tables

3. /* SCREEN=WD*HT */
for (row=0; row<HT; row++) {
//EMAX5A begin tone_curve mapdist=0
for (LOOP0=WD, col=-4; LOOP0--;) {
col += 4;
pix = in[row*WD+col/4];
r = t[ pix>>24 ];
g = t[256+((pix>>16)&255)];
b = t[512+((pix>> 8)&255)];
out[row*WD+col/4]=r<<24 | g<<16 | b<<8;
}
//EMAX5A end
}
//EDMAX5A drain_dirty_lmm
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IMAXのループ構造記述に合わせる
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Color map tables
/* SCREEN=WD*HT */
for (row=0; row<HT; row++) {
for (col=0; col<WD; col++) {
pix = in[row*WD+col];
r = t[ pix>>24 ];
g = t[256+((pix>>16)&255)];
b = t[512+((pix>> 8)&255)];
out[row*WD+col]=r<<24 | g<<16 | b<<8;
} }
Load →
Store ←
Color map tables

4. /* SCREEN=WD*HT */
for (row=0; row<HT; row++) {
//EMAX5A begin tone_curve mapdist=0
for (LOOP0=WD, col=-4; LOOP0--;) {
col += 4;
mop(OP_LDWR, &pix, in_row_WD, col, MSK_W0, in, WD); //pix = in[row*WD+col/4];
mop(OP_LDUBR, &r, t_r, pix, MSK_B3, t, 256*3/4); //r = t[ pix>>24 ];
mop(OP_LDUBR, &g, t_g, pix, MSK_B2, t, 256*3/4); //g = t[256+((pix>>16)&255)];
mop(OP_LDUBR, &b, t_b, pix, MSK_B1, t, 256*3/4); //b = t[512+((pix>> 8)&255)];
out[row*WD+col/4]=r<<24|g<<16|b<<8;
}
//EMAX5A end
}
//EDMAX5A drain_dirty_lmm
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IMAXの高機能関数記述に書き換えながらデバッグする
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Store ←
Color map tables

5. /* SCREEN=WD*HT */
for (row=0; row<HT; row++) {
//EMAX5A begin tone_curve mapdist=0
for (LOOP0=WD, col=-4; LOOP0--;) {
exe(OP_ADD, &col, col, EXP_H3210, 4, EXP_H3210, 0, EXP_H3210); //col += 4;
mop(OP_LDWR, &pix, in_row_WD, col, MSK_W0, in, WD); //pix = in[row*WD+col/4];
mop(OP_LDUBR, &r, t_r, pix, MSK_B3, t, 256*3/4); //r = t[ pix>>24 ];
mop(OP_LDUBR, &g, t_g, pix, MSK_B2, t, 256*3/4); //g = t[256+((pix>>16)&255)];
mop(OP_LDUBR, &b, t_b, pix, MSK_B1, t, 256*3/4); //b = t[512+((pix>> 8)&255)];
exe(OP_MMRG, &out, r, EXP_H3210, g, EXP_H3210, b, EXP_H3210);
mop(OP_STWR, &out, out_row_WD, col, MSK_W0); //out[row*WD+col/4]=r<<24|g<<16|b<<8;
}
//EMAX5A end
}
//EDMAX5A drain_dirty_lmm
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全部書き換えたら逐次実行プログラムとしてデバッグ
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Color map tables

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データの配置と流れの観点から見直す
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Store ←
Color map tables
/* SCREEN=WD*HT */
for (row=0; row<HT; row++) {
//EMAX5A begin tone_curve mapdist=0
for (LOOP0=WD, col=-4; LOOP0--;) {
exe(OP_ADD, &col, col, EXP_H3210, 4, EXP_H3210, 0, EXP_H3210); //col += 4;
mop(OP_LDWR, &pix, in_row_WD, col, MSK_W0, in, WD); //pix = in[row*WD+col/4];
mop(OP_LDUBR, &r, t_r, pix, MSK_B3, t, 256*3/4); //r = t[ pix>>24 ];
mop(OP_LDUBR, &g, t_g, pix, MSK_B2, t, 256*3/4); //g = t[256+((pix>>16)&255)];
mop(OP_LDUBR, &b, t_b, pix, MSK_B1, t, 256*3/4); //b = t[512+((pix>> 8)&255)];
exe(OP_MMRG, &out, r, EXP_H3210, g, EXP_H3210, b, EXP_H3210);
mop(OP_STWR, &out, out_row_WD, col, MSK_W0); //out[row*WD+col/4]=r<<24|g<<16|b<<8;
}
//EMAX5A end
}
//EDMAX5A drain_dirty_lmm

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コンパイル結果
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Store ←
Color map tables

8. int loop=WD/2;
//EMAX5A begin tone_curve mapdist=0
while (loop--) {
mop(OP_LDR, &BR[0][1][1], in++, 0LL, MSK_D0, in, WD, 0, 0, NULL, 0);
mop(OP_LDBR, &BR[1][1][1], t1, BR[0][1][1], MSK_B3, t, 256*3/4, 0, 0, NULL, 0);
mop(OP_LDBR, &BR[1][1][0], t1, BR[0][1][1], MSK_B7, t, 256*3/4, 0, 0, NULL, 0);
mop(OP_LDBR, &BR[1][2][1], t2, BR[0][1][1], MSK_B2, t, 256*3/4, 0, 0, NULL, 0);
mop(OP_LDBR, &BR[1][2][0], t2, BR[0][1][1], MSK_B6, t, 256*3/4, 0, 0, NULL, 0);
mop(OP_LDBR, &BR[1][3][1], t3, BR[0][1][1], MSK_B1, t, 256*3/4, 0, 0, NULL, 0);
mop(OP_LDBR, &BR[1][3][0], t3, BR[0][1][1], MSK_B5, t, 256*3/4, 0, 0, NULL, 0);
exe(OP_CCAT, &r1, BR[1][1][0], EXP_H3210, BR[1][1][1], EXP_H3210, 0, EXP_H3210,OP_NOP,0,OP_NOP,0);
exe(OP_CCAT, &r2, BR[1][2][0], EXP_H3210, BR[1][2][1], EXP_H3210, 0, EXP_H3210,OP_NOP,0,OP_NOP,0);
exe(OP_CCAT, &r3, BR[1][3][0], EXP_H3210, BR[1][3][1], EXP_H3210, 0, EXP_H3210,OP_NOP,0,OP_NOP,0);
exe(OP_MMRG, &r0, r1, EXP_H3210, r2, EXP_H3210, r3, EXP_H3210,OP_NOP,0,OP_NOP,0);
mop(OP_STR, &r0, out++, 0LL, MSK_D0, out, WD, 0, 0, NULL, 0);
}
//EMAX5A end
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2way SIMD版
SIMD Load →
SIMD Store ←
Color map tables

9. 20220202
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2way SIMD版
CCATが増えた
ロード数が３から６に増えた

10. //EMAX5A begin tone_curve mapdist=0
for (CHIP=0; CHIP<NCHIP; CHIP++) { /* output channels are parallelized by multi-chip (OC/#chip) */
/*2*/for (INIT1=1,LOOP1=RMGRP,rofs=0-WD*4; LOOP1--; INIT1=0) { /* stage#0 *//* mapped to FOR() on BR[63][1][0] */
/*1*/for (INIT0=1,LOOP0=WD,cofs=0-4; LOOP0--; INIT0=0) { /* stage#0 *//* mapped to FOR() on BR[63][0][0] */
exe(OP_ADD, &cofs, INIT0?cofs:cofs, EXP_H3210, 4, EXP_H3210, 0LL, EXP_H3210, OP_AND, 0x00000000ffffffffLL, OP_NOP, 0LL); /* stage#0 */
exe(OP_ADD, &rofs, rofs, EXP_H3210, INIT0?WD*4:0, EXP_H3210, 0LL, EXP_H3210, OP_NOP, 0LL, OP_NOP, 0LL); /* stage#0 */
exe(OP_ADD, &pofs, rofs, EXP_H3210, cofs, EXP_H3210, 0LL, EXP_H3210, OP_AND, 0x00000000ffffffffLL, OP_NOP, 0LL); /* stage#1 */
/*map0*/
mop(OP_LDWR, 1, &BR[2][1][1], (Ull)rtop0[CHIP], pofs, MSK_D0, (Ull)rtop0[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#2 */
mop(OP_LDUBR, 1, &BR[3][1][1], (Ull)t1, BR[2][1][1], MSK_B3, (Ull)t1, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#3 */
mop(OP_LDUBR, 1, &BR[3][2][1], (Ull)t2, BR[2][1][1], MSK_B2, (Ull)t2, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#3 */
mop(OP_LDUBR, 1, &BR[3][3][1], (Ull)t3, BR[2][1][1], MSK_B1, (Ull)t3, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#3 */
exe(OP_MMRG, &r1, BR[3][1][1], EXP_H3210, BR[3][2][1], EXP_H3210, BR[3][3][1], EXP_H3210, OP_NOP, 0LL, OP_NOP, 0LL); /* stage#3 */
mop(OP_STWR, 3, &r1, (Ull)dtop0[CHIP], pofs, MSK_D0, (Ull)dtop0[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#3 */
/*map1*/
mop(OP_LDWR, 1, &BR[4][1][1], (Ull)rtop1[CHIP], pofs, MSK_D0, (Ull)rtop1[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#4 */
mop(OP_LDUBR, 1, &BR[5][1][1], (Ull)t1, BR[4][1][1], MSK_B3, (Ull)t1, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#5 */
mop(OP_LDUBR, 1, &BR[5][2][1], (Ull)t2, BR[4][1][1], MSK_B2, (Ull)t2, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#5 */
mop(OP_LDUBR, 1, &BR[5][3][1], (Ull)t3, BR[4][1][1], MSK_B1, (Ull)t3, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#5 */
exe(OP_MMRG, &r1, BR[5][1][1], EXP_H3210, BR[5][2][1], EXP_H3210, BR[5][3][1], EXP_H3210, OP_NOP, 0LL, OP_NOP, 0LL); /* stage#5 */
mop(OP_STWR, 3, &r1, (Ull)dtop1[CHIP], pofs, MSK_D0, (Ull)dtop1[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#5 */
/*map2*/
mop(OP_LDWR, 1, &BR[6][1][1], (Ull)rtop2[CHIP], pofs, MSK_D0, (Ull)rtop2[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#6 */
mop(OP_LDUBR, 1, &BR[7][1][1], (Ull)t1, BR[6][1][1], MSK_B3, (Ull)t1, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#7 */
mop(OP_LDUBR, 1, &BR[7][2][1], (Ull)t2, BR[6][1][1], MSK_B2, (Ull)t2, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#7 */
mop(OP_LDUBR, 1, &BR[7][3][1], (Ull)t3, BR[6][1][1], MSK_B1, (Ull)t3, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#7 */
exe(OP_MMRG, &r1, BR[7][1][1], EXP_H3210, BR[7][2][1], EXP_H3210, BR[7][3][1], EXP_H3210, OP_NOP, 0LL, OP_NOP, 0LL); /* stage#7 */
mop(OP_STWR, 3, &r1, (Ull)dtop2[CHIP], pofs, MSK_D0, (Ull)dtop2[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#7 */
/*map3*/
mop(OP_LDWR, 1, &BR[8][1][1], (Ull)rtop3[CHIP], pofs, MSK_D0, (Ull)rtop3[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#8 */
mop(OP_LDUBR, 1, &BR[9][1][1], (Ull)t1, BR[8][1][1], MSK_B3, (Ull)t1, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#9 */
mop(OP_LDUBR, 1, &BR[9][2][1], (Ull)t2, BR[8][1][1], MSK_B2, (Ull)t2, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#9 */
mop(OP_LDUBR, 1, &BR[9][3][1], (Ull)t3, BR[8][1][1], MSK_B1, (Ull)t3, 256/8, 0, 0, (Ull)NULL, 256/8); /* stage#9 */
exe(OP_MMRG, &r1, BR[9][1][1], EXP_H3210, BR[9][2][1], EXP_H3210, BR[9][3][1], EXP_H3210, OP_NOP, 0LL, OP_NOP, 0LL); /* stage#9 */
mop(OP_STWR, 3, &r1, (Ull)dtop3[CHIP], pofs, MSK_D0, (Ull)dtop3[CHIP], WD*RMGRP/2, 0, 0, (Ull)NULL, WD*RMGRP/2);/* stage#9 */
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3重ループをIMAXの1回の起動に写像する
実際には、#define tone_core1(r, rm1, rp1)
などと定義して並べるので、こんな冗長な書き方は不要だが、
最初なのでブラックボックス無しで説明

11. 20220202
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3重ループをIMAXの1回の起動に写像する

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この先を知りたい人は…