3. Exceptions Overview
The ARM v7-M (and v6-M) exception architecture is very different from
other ARM architectures
Designed for microcontroller applications
– Support for many interrupt sources
– Efficient handling of nested interrupts
– Flexible interrupt architecture (highly configurable)
– Built in RTOS support
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– Built in RTOS support
Main Features
– Nested Vector Interrupt Controller (NVIC)
– Micro-coded architecture handles the “dirty work”
– No software overhead for Interrupt Entry/Exit and Interrupt Nesting
– Only one mode and one stack for all exception handling
– Handler mode / Main stack
– Easy to program
– All exception handlers may be coded in “C”
5. Interrupt Arrival During State Restore
Traditional interrupt handling
must complete stack cycle
IRQ1
IRQ2
Higher Priority
26 cycles16 cycles
Interrupt routine Pop Push Interrupt routine
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PopCortex-M3 or Cortex-M4 may
abandon stack operations
dynamically
Load Multiple uninterruptible, and hence
the core must complete the POP and
then full stack PUSH
POP may be abandoned early if another
interrupt arrives
If POP is interrupted it only takes 6
cycles to enter ISR2 (equivalent to Tail-
chaining)
ARM7 ARM Cortex-M3 or ARM Cortex-M4
6 cycles1-10 cycles
Interrupt routine TC Interrupt routine
6. Exception Types
Exceptions can be caused by various events
– Internal
– External
ARM Processor
Application CodeInternal External
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Thread
Mode
Application Code
Handler
Mode
Exception Code
SVC
PendSV
Faults
SysTick
Internal
Exceptions
Reset
Interrupts
Faults
External
Exceptions
7. Processor Mode Usage
Processor mode may change when exceptions occur
– Thread Mode is entered on Reset
– Handler Mode is entered on all other exceptions
ARM Processor
Application Code
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Thread
Mode
Application Code
Handler
Mode
Exception Code
SVC
PendSV
Faults
SysTick
Exception
Return
Reset
Interrupts
Faults
8. External Interrupts
External Interrupts handled by Nested Vectored Interrupt Controller (NVIC)
– Tightly coupled with processor core
One Non-Maskable Interrupt (NMI) supported
Number of external interrupts is implementation-defined
– ARMv7-M supports up to 496 interrupts
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– ARMv7-M supports up to 496 interrupts
……
Cortex-Mx
Processor Core
INTISR[0]
…
…
INTISR[N]
INTNMI
NVIC
Cortex-Mx Integration Layer
9. Micro-coded Interrupt Mechanism
Interrupt architecture designed for low latency
Interrupt prioritization mechanism is built into NVIC
Interrupt entry/exit is “micro-coded” – controlled by
hardware
– Automatically saves and restores processor context
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– Allows late determination of highest priority pending interrupt
– Allows another pending interrupt to be serviced without a full
restore/save of processor state (tail-chaining)
– Interrupt Service Routines (ISRs) can be written entirely in C
Some multi-cycle instructions are interruptible for
improved interrupt latency
10. Exception Model
Core begins execution with a “base” execution priority level
– At reset all interrupts are disabled
– The base execution priority level has a lower priority than the lowest programmable
priority level, so any enabled interrupt will pre-empt the core
When an enabled interrupt is asserted
– Interrupt is taken (serviced by interrupt handler)
– Core runs the handler at the execution priority level of the interrupt
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– When interrupt handler completes, original priority level is restored
When an enabled interrupt is asserted with lower or equal priority
– Interrupt is “pended” to run (when it has sufficient priority)
When a disabled interrupt is asserted
– Interrupt is “pended” to run (when it is enabled and has sufficient priority)
Interrupt nesting is always enabled
– To avoid nesting set all interrupts to the same priority
12. Exception Priorities Overview
Name Exception Number Exception Priority No.
Interrupts #0 - #495 (N interrupts) 16 to 16 + N 0-255 (programmable)
SysTick 15 0-255 (programmable)
PendSV 14 0-255 (programmable)
SVCall 11 0-255 (programmable)
Usage Fault 6 0-255 (programmable)
Bus Fault 5 0-255 (programmable)
Lowest
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The lower the priority number, the higher the priority level
Priority level is stored in a byte-wide register, which is set to 0x0 at reset
Exceptions with the same priority level follow a fixed priority order using the exception
number
– Lower exception number has higher priority level
Bus Fault 5 0-255 (programmable)
Memory Management Fault 4 0-255 (programmable)
Hard Fault 3 -1
Non Maskable Interrupt (NMI) 2 -2
Reset 1 -3 Highest
13. Pre-emption
Pre-emption occurs when a task is abandoned in order to handle an
exception
The currently running instruction stream is pre-empted
Pre-emption rules
– When multiple exceptions with the same priority are pending, the one with
the lowest exception number takes place
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the lowest exception number takes place
– Once an exception is active, only exceptions with a higher priority can pre-
empt it
“Late arrival” is a little different
– In this case, a higher-priority exception takes the place of a lower one after
the exception entry sequence has started
– More later...
16. Vector Table for ARMv7-M
First entry contains initial Main SP
All other entries are addresses for
exception handlers
– Must always have LSBit = 1 (for Thumb)
Table has up to 496 external interrupts
– Implementation-defined
– Maximum table size is 2048 bytes
16 + N
…
16
15
14
13Reserved
PendSV
SysTick
External 0
…
External N0x40 + 4*N
…
0x40
0x3C
0x38
0x34
Address Exception #
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– Maximum table size is 2048 bytes
Table may be relocated
– Use Vector Table Offset Register
– Still require minimal table entries at 0x0 for
booting the core
Each exception has an exception number
– Used in Interrupt Control and State
Register to indicate the active or pending
exception type
Table can be generated using C code
– Example provided later
Reserved (x4)
Usage Fault
Mem Manage Fault
Hard Fault
NMI
Reset
Initial Main SP
0x1C to 0x28
0x18
0x14
0x10
0x0C
0x08
0x04
0x00
12
11SVC
Debug Monitor
Bus Fault
0x30
0x2C
7-10
6
5
4
3
2
1
N/A
17. Reset Behavior
Reset Handler
4
3
Main
5
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1. A reset occurs (Reset input was asserted)
2. Load MSP (Main Stack Pointer) register initial value from address 0x00
3. Load reset handler vector address from address 0x04
4. Reset handler executes in Thread Mode
5. Optional: Reset handler branches to the main program
0x04
0x001 Initial value of MSP
Reset Handler Vector
r13 (MSP)
2
18. Exception Behavior
Exception Handler
2
3
Main
1
4
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1. Exception occurs
– Current instruction stream stops
– Processor accesses vector table
2. Vector address for the exception loaded from the vector table
3. Exception handler executes in Handler Mode
4. Exception handler returns to main (assuming no nesting – more later)
Exception Vector
19. Exception States
Exceptions can be in the following states
– Inactive: Not Pending or Active
– Pending: Exception event has been generated but processing has not started yet
– Active: Exception processing has been started but is not complete yet
– An exception handler can interrupt the execution of another exception handler. In
this case both exceptions are in the active state.
– Active and Pending: The exception is being serviced by the processor and there is
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– Active and Pending: The exception is being serviced by the processor and there is
a pending exception from the same source
Inactive
Pending
Active
20. Interrupt Service Routine Entry (1)
When receiving an interrupt the processor will finish the current instruction
for most instructions
– To minimize interrupt latency, the processor can take an interrupt during the
execution of a multi-cycle instruction - see next slide
Processor state automatically saved to the current stack
– 8 registers are pushed: PC, R0-R3, R12, LR, xPSR
– Follows ARM Architecture Procedure Calling Standard (AAPCS)
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– Follows ARM Architecture Procedure Calling Standard (AAPCS)
During (or after) state saving the address of the ISR is read from the Vector
Table
Link Register is modified for interrupt return
First instruction of ISR executed
– For Cortex-M3 or Cortex-M4 the total latency is normally 12 cycles, however,
interrupt late-arrival and interrupt tail-chaining can improve IRQ latency
ISR executes from Handler mode with Main stack
21. Interrupt Service Routine Entry (2)
On taking an exception during a multi-cycle instruction the processor either:
– Continues execution of the instruction after returning from the exception
– Abandons the instruction and restarts the instruction on returning from the exception
For multi-cycle instructions on the Cortex-M3 and Cortex-M4 processors:
– Divide, multiply and load/store double instructions are abandoned and restarted
– Load/store multiple instructions are treated as “exception-continuable instructions”, if
possible
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possible
– The ICI bits in the EPSR are used to hold the continuation state
– However, in some situations LDM/STM instructions are abandoned and restarted
– For example, An LDM/STM instruction within an If-Then block
Architecturally software must not use an LDM/STM to access a volatile location
– The Cortex-M3/M4 processors must not use an LDM/STM to access a volatile location if
– it executes inside an IT block
– it loads the same register as the base register
– it loads the PC
22. Interrupt Stacking
Foreground stack (Main or Process) used to
store the pre-interrupt state
Stack is Full-Descending
– SP automatically decremented on push
– SP always points to non-empty value
– Same behavior as other ARM cores
:
<old TOS>
Old SP
xPSR
ReturnAddress
LR
R12
SP
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The stack must be 8-byte aligned
– AAPCS compliant
– STKALIGN bit in Configuration and Control
Register should be set to 1
– Extra word padded to stack if required
Main stack active after state is saved
ISR can be coded in “C”
– No prologue code required (no overhead)
:
:
:
R12
R3
R2
R1
R0
0x0
23. Returning From Interrupt
Can return from interrupt with the following instructions when the PC is
loaded with “magic” value of 0xFFFF_FFFX (same format as
EXC_RETURN)
– LDR PC, …..
– LDM/POP which includes loading the PC
– BX LR (most common)
If no interrupts are pending, foreground state is restored
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If no interrupts are pending, foreground state is restored
– Stack and state specified by EXC_RETURN is used
– Context restore on ARM Cortex-M3 and ARM Cortex-M4 requires 10 cycles
If other interrupts are pending, the highest priority may be serviced
– Serviced if interrupt priority is higher than the foreground’s base priority
– Process is called Tail-Chaining as foreground state is not yet restored
– Latency for servicing new interrupt is only 6 cycles on M3/M4 (state already saved)
If state restore is interrupted, it is abandoned
– New ISR executed without state saving (original state still intact and valid)
– Must still fetch new vector and refill pipeline (6-cycle latency on M3/M4)
24. Nesting Example
Higher Priority
Base CPU
IRQ2
IRQ1
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Core Execution
Base CPU
Time
Foreground ISR2 ISR1 ISR2 ForegroundPop Pop
IRQ1 Active
IRQ2 Active
Pop
Interrupt entry requires 12 cycles
Interrupt exit requires 10 cycles
Push Push
Push
25. Tail Chaining Example
Higher Priority
Base CPU
IRQ2
IRQ1
Time
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Core Execution
Base CPU
Foreground ISR1 ISR2
Time
TC Pop
IRQ1 Active IRQ2 Active
Tail Chaining requires 6 cycles
Push Foreground
TC
26. Late Arriving Example
Higher Priority
Base CPU
IRQ2
IRQ1
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Core Execution
Base CPU
Time
Foreground ForegroundPopISR1 ISR2
A pending higher priority exception is handled before an already
pending lower priority exception even after exception entry sequence
has started
The lower priority exception is handled after the higher priority
exception
Push TC
28. Disabling Interrupts (Priority
Boosting)
Priority Boosting raises the base
level of execution priority level to 0
This disables interrupts by
preventing all programmable
exceptions from activating
The Priority Mask Register is used
Programmable
Exceptions
0x80
0xC0
Lowest
Priority
Priority
Boosting
Activation
Prevented
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The Priority Mask Register is used
to disable interrupts ...
Reset
NMI
Fault
0x00
-1
-2
-3
0x40
Highest
Priority
“Base” Execution
29. Priority Boosting
Three methods to set the Execution Priority via software on v7-M
BASEPRI register sets execution priority level from 1 to N (N=lowest priority)
– Acts as a general interrupt mask
– Example
– BASEPRI = 16 only interrupts with priority levels (-2 to 15) can pre-empt
– If BASEPRI = 0 masking is disabled (any enabled interrupt pre-empts the core)
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– If BASEPRI = 0 masking is disabled (any enabled interrupt pre-empts the core)
PRIMASK bit sets the execution priority level to 0
– Only allows Hard Fault and NMI to pre-empt
FAULTMASK bit sets the execution priority level to -1
– Can only be set by an exception handler (auto clears on exception return)
– Only allows NMI to pre-empt
30. Priority Boosting Instructions
BASEPRI is accessed like a Program Status Register
MSR{cond} BASEPRI, Rm ; write BASEPRI
MRS{cond} Rd, BASEPRI ; read BASEPRI
PRIMASK and FAULTMASK map to the classic “I” and “F” flags
CPSID I ; set PRIMASK (disable interrupts)
CPSIE I ; clear PRIMASK (enable interrupts)
CPSID F ; set FAULTMASK (disable faults and interrupts)
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CPSID F ; set FAULTMASK (disable faults and interrupts)
CPSIE F ; clear FAULTMASK (enable faults and interrupts)
RVCT Intrinsics
– PRIMASK
__enable_irq(), __disable_irq()
– FAULTMASK
__enable_fiq(), __disable_fiq()
Must be in privileged mode to modify execution priority level
31. v7-M Priority Grouping
The 8-bit Priority Level is divided into 2 fields
– Group Priority and Sub-Priority [GROUP.SUB]
Group Priority is the pre-empting priority level
Sub-Priority is used only if the Group Priority is the same
Exception Number is final tie-breaker
– If two interrupts have identical priority levels, lowest vector number takes priority
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Example
– 4-bit Group Priority / 4-bit Sub-Priority
– SysTick is enabled with priority = 0x30
– Timer1 is enabled with priority = 0x30
– Timer2 is enabled with priority = 0x31
– If Timer1 & Timer2 assert simultaneously Timer1 serviced, Timer2 pended
– If Timer2 is being serviced and Timer1 asserts Timer1 pended
– If SysTick & Timer1 assert simultaneously SysTick serviced, Timer1 pended
bit4
SubGroup
bit7 bit3 bit0
32. Group Priority / Sub-Priority Selection
PRIGROUP
Binary Point
(group.sub)
Group Priority
(Pre-empting)
Sub-Priority
Bits Levels Bits Levels
000 7.1 gggggggs 7 128 1 2
001 6.2 ggggggss 6 64 2 4
010 5.3 gggggsss 5 32 3 8
011 4.4 ggggssss 4 16 4 16
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Selection made by PRIGROUP in Application Interrupt and Reset Control Reg
System-wide configuration applies to all interrupt priorities
If less than 8 priority bits implemented, fewer Sub-Priority bits are available
– Example: 6 priority bits and PRIGROUP = 001 6 Group Bits / 0 Sub-Priority Bits
011 4.4 ggggssss 4 16 4 16
100 3.5 gggsssss 3 8 5 32
101 2.6 ggssssss 2 4 6 64
110 1.7 gsssssss 1 2 7 128
111 0.8 ssssssss 0 0 8 256
33. Interrupt Control and Status Bits
ENABLE bit (R/W) – is interrupt enabled or disabled?
PENDING bit (R/W) – is interrupt waiting to be serviced?
– Interrupt is pending if priority is too low or if interrupt is disabled
– Can set bit to generate an interrupt (if enabled and sufficient priority)
– Can clear bit to clear a pending interrupt (interrupt will not be serviced)
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ACTIVE bit (R only) – is interrupt active or inactive?
– If interrupts are nested, more than one active bit will be set
PRIORITY bits (R/W) – set the interrupt priority
– Lower value has higher priority (priority 0 is highest)
– ARMv7-M: 3 - 8 bits (8 - 256 levels)
– May be divided into a group (pre-empt) priority and a sub-group priority
(user defined)
36. The vector table at address
0x0 is minimally required to
have 4 values: stack top,
reset routine location,
NMI ISR location,
HardFault ISR location
Vector Table in C
typedef void(* const ExecFuncPtr)(void) __irq;
#pragma arm section rodata="exceptions_area”
ExecFuncPtr exception_table[] = {
(ExecFuncPtr)&Image$$ARM_LIB_STACK$$ZI$$Limit, /* Initial SP */
(ExecFuncPtr)__main, /* Initial PC */
NMIException,
HardFaultException,
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HardFaultException,
MemManageException,
BusFaultException,
UsageFaultException,
0, 0, 0, 0, /* Reserved */
SVCHandler,
DebugMonitor,
0, /* Reserved */
PendSVC,
SysTickHandler
/* Configurable interrupts start here...*/
};
#pragma arm section
Once interrupts are
enabled, the vector
table (whether at 0
or in SRAM) must
then have pointers
to all enabled (by
mask) exceptions
The SVCall ISR
location must be
populated if the SVC
instruction will be
used
37. Writing Interrupt Handlers (1)
Clear the interrupt source if required
– Some may not need to be cleared (like SysTick)
Interrupt nesting always enabled by default
– No modification needed to interrupt handlers
– Just be careful of Main stack overflows
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STKALIGN bit should be set to 1 to ensure 8-byte stack alignment
on exception entry
– Bit 9 in Code Configuration Register (a read-only register on latest revisions
of ARM Cortex-M3)
38. Writing Interrupt Handlers (2)
C Code is recommended for all handlers
– ISR function must be type void and can not accept arguments
– The __irq keyword is optional (but recommended for clarity)
__irq void SysTickHandler (void) {
}
– No special assembly language entry and exit code required
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No special assembly language entry and exit code required
Writing handlers in assembly
– Must manually save and restore any non-scratch registers which are used
– R4, R5, R6, R7, R8, R9, R10, R11, LR
– Must maintain 8-byte stack alignment if making function calls
– Must return from interrupt using EXC_RETURN with proper instruction
– LDR PC, …..
– LDM/POP which includes loading the PC
– BX LR
40. Internal Exceptions
SysTick Timer
– Provides system heart-beat for RTOS (or custom program executive)
– Periodic interrupt drives system task scheduling
– Better than a standard Timer Interrupt
– Integrated into the NVIC
– Does not vary between vendor implementation and Cortex-M families
System Service Call (SVC)
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System Service Call (SVC)
– Similar to “SVC” instruction on other ARM cores
– Allows non-privileged software to make system calls
– RTOS services requests from non-privileged mode
– Provides protection to important system functionality
– Examples: Open Serial Port, Remap Memory, Enter Low Power Mode, etc.
Pended System Call (PendSV)
– Operates with SVC to ease RTOS development
– Intended to be an interrupt for RTOS use
41. SysTick Timer
24-bit count down timer
2 clock sources
– Internal core clock / external clock (STCLK)
2 modes
– Generate interrupt / do not interrupt
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– Generate interrupt / do not interrupt
Can be used as a general timer
Programmer’s Interface
– Control and Status Register – sets mode and has self-clearing overflow bit
– Reload Value Register – sets the SysTick period
– Current Value Register – shows current SysTick value
– Calibration Value Register – for configuring a 10 msec period
42. Pended System Call (PendSV)
Permanently enabled interrupt
– Avoids need for long periods of interrupts disabled
Not an instruction – but instigated via Interrupt Control State
Register
– May only be written in privileged mode
– Set by PENDSVSET bit
–
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– Cleared by PENDSVCLR bit
Intended usage
– As a private, low-level interrupt for the RTOS
– SVC cannot be nested, so RTOS uses PendSV to perform specific tasks
– SVC and PendSV are given same interrupt priority…
– PendSV will only run after SVC completes (and before foreground is
returned)
– PendSV can then handle low-priority RTOS “cleanup” or perform context
switch
43. Fault Exceptions on v7-M
Three classes of faults
– Bus – Memory access error (Prefetch or Data Access)
– Memory Manage – MPU permissions mismatch
– Usage – Undefined instruction, CP access, illegal state transition (i.e. T=0)
– Can optionally trap divide by zero and unaligned memory accesses
Bus, Memory Manage and Usage Faults
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Bus, Memory Manage and Usage Faults
– Manually enabled in the System Handler Control and State Register
– Disabled by default – only enable if required
– User-defined priority level
Hard Fault – “Fall Back” Fault
– Always enabled with priority level “-1”
– Executes through “Fault Escalation”
44. Fault Escalation
Fault Escalation to Hard Fault occurs when a fault occurs but…
– The fault is not enabled or…
– The handler doesn’t have enough priority to run or…
– The fault handler encounters the same fault
Examples
– An undefined instruction is decoded
– The ARM Cortex-M3 and ARM Cortex-M4 try to signal a Usage Fault, but the
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– The ARM Cortex-M3 and ARM Cortex-M4 try to signal a Usage Fault, but the
UsageFault is not enabled
– With the MPU enabled an interrupt handler makes an illegal memory access
– The ARM Cortex-M3 and ARM Cortex-M4 try to signal a Memory Manage Fault, but
the Fault priority is lower than the priority of the running interrupt
– An undefined instruction is encountered in a UsageFault handler
– An enabled fault handler causes the same kind of fault as is being serviced
45. Other Interrupt & Exception
Information
You should also be familiar with…
– Instructions/functions for changing PRIMASK, FAULTMASK, BASEPRI
– Format and usage of Interrupt Enable, Active, Pending and Priority registers
– Format and interpretation of EXC_RETURN values
– Fault handling & Fault escalation
– The Lockup state
–
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– Edge and Level Sensitive Interrupt Configuration
49. Memory Protection Overview
MPU architecture same as ARM Cortex-R4 - ARM v7 PMSA
Supports 8 regions
– Each region applies to both instruction and data accesses (unified regions)
Access controlled by region attributes
– Individual Instruction access, Data access and Memory attributes
– Controls Cacheability, Data/Peripheral Type selection
Regions have variable base address and size
– Base address must be aligned to the region size boundary
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Regions may overlay other regions
MPU is optional
– Absent or disabled MPU uses the default memory map
Sub-regions also possible within each region
MPU can modify some attributes of the default memory map
– Cannot modify addresses of Code or System spaces
– Top 0.5GB of the memory map is always “Execute Never”, so cannot be changed by MPU
– Bit-Band regions (if implemented) cannot be moved
– PPB is always strongly-ordered
MPU primarily provides access protection
– Can also make Peripheral memory partitions executable
50. Region Overview
Each region consists of:
– Base address
– Region Attribute and Size
– Memory Type and Access Control
At least one region must be defined (or PRIVDEFENA set) before enabling the MPU
– No regions defined or enabled after reset
– Accesses that do not fall into any region cause an abort, unless privileged and PRIVDEFENA is set
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– Region 0 lowest priority
– Code enabling MPU must be included in an executable region
– Otherwise, core will continually abort
– If MPU enabled, only System space (SCB) and vector table loads are guaranteed to be available
– Other accesses depend upon region settings and PRIVDEFENA
Base address must always be aligned to the region size
MPU regions are set up through the MPU registers in the SCB
51. Sub-Regions
Each region can be split into 8 equal sized non-overlapping sub-regions
– Allows the granularity of protection and memory attributes to be increased without
significant increase in hardware complexity
– Reduces the number of regions which must be used to align protection boundaries to
non-naturally aligned addresses
Each region has 8 sub-region disable bits
– Sub-region disable bit=0, sub region described as part of the region
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– Sub-region disable bit=0, sub region described as part of the region
– Protection and memory type attributes of the region apply to that sub-region
– Sub-region disable bit=1, sub region described as not part of the region
– Address covered by that sub-region is not matched as part of the region
Sub-regions being disabled enables backward compatibility with ARMv6
All region sizes between 256bytes and 4Gbytes support 8 sub-regions
Region sizes below 256bytes do not support sub-regions
52. Further MPU Information
You should also be familiar with…
– Region overlapping and sub regions
– Memory types and type extensions
– Access permissions
– MPU Alias Registers
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54. The SysTick Timer
Inclusion of the timer is implementation-defined in ARMv6-M
– Mandatory in ARMv7-M
Provides internal System Timer (SysTick)
– And a related SysTick exception
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– And a related SysTick exception
SysTick can be used in different ways
– Simple counter
– RTOS tick timer
– Dynamic clock management
55. The System Timer - SysTick
SysTick is a 24-bit counter
– Decrementing
– Clear-on-write
– Reload-on-zero
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Flexible control mechanism
– Using 4 registers
56. SysTick Registers
SysTick Control and Status
– Configure clock
– Enable the counter
– Enable the SysTick interrupt
– Determine counter status
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SysTick Reload value
– Counter wrap value
SysTick Current value
SysTick Calibration value
57. Basic SysTick Operation
1. Reload counter using Reload register
2. Enable/disable counter using Control & Status
– Current value is decremented when enabled until 0 is reached
– Can generate a counter event – e.g. SysTick Interrupt
3. Counter is auto-reloaded when value is 0 on wrap-around
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Reload
0x100000
Current
0x100000
0x000000Wrap
around
Counter
EventControl&Status
58. SysTick Clocks
Control & Status specifies which clock should be used by the counter
Core clock
– When no external reference clock is provided (NOREF)
External reference clock
– Can be provided by the implementation
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ARM Processor
Current
clock
Control&Status
Core
Clock
External
Reference
Clock
59. SysTick Calibration
Calibration can be used to allow code to measure real-time intervals in a
standard way
– Implementation-independent
2 clock sources can be implemented
– External reference clock
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– Internal clock
SysTick Calibration Value register provides information for calibration
– Reload value to count 10ms (TENMS)
– Possibility to mark the 10ms as inexact (SKEW)
– Due to rounding
60. Calibration - TENMS
Provides a 10ms reference timing for the SysTick counter
– Can be loaded directly into the Reload Value register
– Software can scale the counter to desired clock rates
– Reload value = (factor * (TENMS + 1)) - 1
Ensures a 10ms cycle of the SysTick counter
– Can be used for real-time applications
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If TENMS is 0
– No 10ms reference value is provided
– Reference clock is not constant
10ms (100Hz)
1kHz
2kHz
TENMS = 9, or 0x9
TENMS = 19, or 0x13
61. Calibration - SKEW
Provides information if the TENMS value is exact to the reference
clock
SKEW = 0
– No skew, 10ms can be exactly represented
SKEW = 1
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SKEW = 1
– 10ms cannot be exactly represented
10ms
1kHz
1.05kHz
SKEW=0
SKEW=1 9.5 TENMS
9 TENMS
