Chapter 4 Boylstead DC Biasing-BJTs.pptx

Chapter 4
DC Biasing–BJTs Dr. Jehangir Arshad

Biasing
Biasing: DC voltages applied to a transistor in order to turn it on so that it can amplify the ACsignal.
When transistor is biased, we establish certain current and voltage conditions of transistor
(operating conditions or DC operating point or Q-Point )
Important to keep operating point stable for proper working of transistor.
Recall the following basic relationships for a transistor:
VBE  0.7 V
IE  ( 1)I
IC  I
Transistor amplifier design needs knowledge of both dc and ac response of the system
“Improved output ac power level is the result of a transfer of energy from the applied dc
supplies”
Analysis or design of any electronic amplifier has two components:
 The DC portion and
 AC portion

Operating Point
The DC input
establishes an
operating or
quiescent point
called the Q-point.
Various operating points within the limits of operation of a transistor.
Electronic Devices and Circuit Theory, 10/e
Robert L. Boylestad and Louis Nashelsky
Copyright ©2009 by Pearson Education,Inc.
Upper Saddle River, New Jersey 07458 • All rights reserved.
3

Figure Description
 Horizontal line for the maximum collector current (ICmax ) and a vertical line at
the maximum collector-to-emitter voltage VCEmax.
 Maximum power constraint is defined by the curve (PCmax ) in the same figure.
 At the lower end of the scales are the cutoff region , defined by (IB <= 0
microA), and the saturation region , defined by (VCE <= VCEsat) .
 BJT device could be biased to operate outside these maximum limits, but the
result of such operation would be either a considerable shortening of the
lifetime of the device or destruction of the device.
 Confining ourselves to the active region, we can select many different operating
areas or points and chosen Q -point often depends on the intended use of the
circuit.

Figure Description
 No bias Point A: Device will completely off, resulting in a Q point
at A — namely, zero current through the device (and zero voltage
across it).
It is necessary to bias a device so that it can respond to the entire
range of an input signal, point A would not be suitable.
Point B: signal is applied, device will vary in current and voltage
from the operating point, allowing the device to react to (and
possibly amplify) both the positive and negative excursions of the
input signal.
If input signal is properly chosen, voltage and current of device will
vary, but not enough to drive the device into cutoff or saturation.

Figure Description
 Point C: allow some positive and negative variation of the output signal, but the peak-to-
peak value would be limited by the proximity of VCE = 0 V and IC = 0 mA.
 Operating at point C also raises some concern about the non-linearities introduced by the
fact that the spacing between IB curves is rapidly changing in this region.
 In general, it is preferable to operate where the gain of the device is fairly constant (or
linear) to ensure that the amplification over the entire swing of input signal is the same.
Point B is a region of more linear spacing and therefore more linear operation, as shown
in Fig.

 Point D: sets the device operating point near the maximum voltage and power level.
 The output voltage swing in the positive direction is thus limited if the maximum voltage
is not to be exceeded.
 Point B: therefore seems the best operating point in terms of linear gain and largest
possible voltage and current swing. This is usually the desired condition for small-signal
amplifiers but not the case necessarily for power amplifiers.

Three States of Operation
• Active or Linear Region Operation Base–Emitter junction is
forward biased Base–Collector junction is reverse biased
• Cutoff Region Operation
Base–Emitter junction is reverse biased
• Saturation Region Operation
Base–Emitter junction is forward biased Base–
Collector junction is forward biased
7

DC Biasing Circuits
8
• Fixed-bias circuit
• Emitter-stabilized bias circuit
• Collector-emitter loop
• Voltage divider bias circuit
• DC bias with voltage feedback

Fixed Bias configuration
9

Fixed Bias configuration
Fixed bias circuit
10
DC equivalent

The Base-Emitter Loop
From Kirchhoff’s voltage
law:
+VCC – IBRB – VBE = 0
Solving for base current:
R B
 VB E
IB 
VCC
11

Collector-Emitter Loop
Collector current:
I  IB
C
From Kirchhoff’s voltage law:
VCE  VCC  ICRC
12

Example 4.1
Find IBQ , ICQ , VCEQ , VB
, VC , VBC.
Dr. Talal Skaik 2014 13

Transistor Saturation
 For a transistor operating in the saturation region, the current is a maximum value for the
particular design. Change the design and the corresponding saturation level may rise or
drop.
 Of course, the highest saturation level is defined by the maximum collector current as
provided by the specification sheet.
 Saturation conditions are normally avoided because the base–collector junction is no
longer reverse-biased and the output amplified signal will be distorted.
 Note that it is in a region where the characteristic curves join and the collector-to-emitter
voltage is at or below VCEsat.
 In addition, the collector current is relatively high on the characteristics
 Icsat = Vcc/Rc

Load Line Analysis
VCE
15
VCC IC RC

Load Line Analysis
VCE VCC  IC RC
C
16
C
VCE
I
R
IC 0mA
VCE 0V
VCC

VCC

Load Line Analysis
17
Movement of the Q-point with increasing level of IB.
(The level of IB is changed by varying the value of RB)

Load Line Analysis
18
Effect of an increasing level of RC on the load line and the Q-point.
(VCC fixed)

Load Line Analysis
19
Effect of lower values of VCC on the load line and the Q-point.

Example 4.3
20
Find VCC , RC , RB for
the fixed biasing
configuration

Emitter-Bias Circuit
Adding a resistor
(RE) to the emitter
circuit stabilizes the
bias circuit.

Base-Emitter Loop
VCC -VBE
22
RB  ( 1)RE
IB 
 VCC - IERE - VBE - IERE  0
Since IE = ( +1)IB:
VCC - IBRB - ( 1)IBRE  0
Solving for IB:
Difference of fixed bias and this arrangement is = ( 1)RE

Collector-Emitter Loop
23
IERE  V  I R  V  0
CE C C CC
Since IE  IC:
VCE  VCC – IC (RC  RE )
Also:
VE IERE
VC  VCE  VE  VCC - ICRC
VB  VCC – I R RB  VBE  VE

Example 4.4
Find IB , IC , VCE , VC , VE , VB , VBC .

Improved Biased Stability
Stability refers to a circuit condition in which the
currents and voltages will remain fairly constant over
a wide range of temperatures and transistor Beta ()
values.
Adding RE to the emitter improves the stability of atransistor.
25
Transistor Saturation
𝐼𝐶𝑠𝑎𝑡
=
𝑉
𝑐𝑐
𝑅𝑐 + 𝑅𝐸

Improved Biased Stability
26

Load Line Analysis
VCE VCC  IC (RC RE )
C
C
VCE
VCC
IC 0mA
E VCE 0V
VCC
I 
R  R
27

Voltage Divider Dias
29
 n the previous bias configurations the bias current ICQ and voltage VCEQ were
a function of the current gain b of the transistor.
 However, because b is temperature sensitive, especially for silicon transistors, and
the actual value of beta is usually not well defined, it would be desirable to develop
a bias circuit that is less dependent on, or in fact is independent of, the transistor
beta.
 The voltage-divider bias configuration given in next slides is such a network.
 If analyzed on an exact basis, the sensitivity to changes in beta is quite small. If the
circuit parameters are properly chosen, the resulting levels of ICQ and VCEQ can be
almost totally independent of beta.

30
 There are two methods that can be applied to analyze the voltage-divider
configuration.
 First to be demonstrated is the exact method, which can be applied to any voltage-
divider configuration.
 Second is referred to as the approximate method and can be applied only if specific
conditions are satisfied. The approximate approach permits a more direct analysis
with a savings in time and energy.
 All in all, the approximate approach can be applied to the majority of situations and
therefore should be examined with the same interest as the exact method.

31

Voltage Divider Dias (Exact Analysis)
32

33

Voltage Divider Dias (Approximate Analysis)
34

35
Transistor Saturation:
=
𝑉
𝑐𝑐
𝑅𝑐 + 𝑅𝐸
Load Line Analysis:

36
Example 4.9
Analysis of Fig. 4 .35 using the approximate technique, and compare
solutions for 𝐼𝑐𝑄
𝑎𝑛𝑑𝑉𝐶𝐸𝑄
?

COLLECTOR FEEDBACK CONFIGURATION
37

38
Base–Emitter Loop

39
Base–Emitter Loop

40
Collector – Emitter Loop

41

42
Transistor Saturation:
=
𝑉
𝑐𝑐
𝑅𝑐 + 𝑅𝐸
Load Line Analysis:
Continuing with the approximation I’C = IC results in the same load line defined for the
voltage-divider and emitter-biased configurations. The level of IBQ is defined by the
chosen bias configuration.

43

Emitter Follower Configuration
44

Emitter Follower Configuration
45

Common Base Configuration
46

Common Base Configuration
47

MISCELLANEOUS BIAS CONFIGURATIONS
48
There are a number of BJT bias configurations that do not match the basic mold of those
analyzed in the previous sections.
In fact, there are variations in design that would require many more pages than is possible in
a single publication.
However, the primary purpose here is to emphasize those characteristics of the device that
permit a dc analysis of the configuration and to establish a general procedure toward the
desired solution.
For each configuration discussed thus far, the first step has been the derivation of an
expression for the base current. Once the base current is known, the collector current and
voltage levels of the output circuit can be determined quite directly. This is not to imply that
all solutions will take this path, but it does suggest a possible route to follow if a new
configuration is encountered.

49

Chapter 4 Boylstead DC Biasing-BJTs.pptx

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