Computer Organization : CPU, Memory and I/O organization

Unit 5
CPU,MEMORY
AND I/O
ORGANISATION

Which Computer should I purchase?

WiFi?
Bluetooth?
Graphics
Card?
e
Memory?
Speed?

1.The Processor Unit (CPU):
• It is the brain of the computer system.
• All major calculation and comparisons are made
inside the CPU and it is also responsible for
activation and controlling the operation of other
unit.
• This unit consists of two major components, that are
arithmetic logic unit (ALU) and control unit (CU).

2. Input / Output Unit:
• The input/output unit consists of devices used to
transmit information between the external world
and computer memory.
• The information fed through the input unit is stored
in computer's memory for processing and the final
result stored in memory can be recorded or display
on the output medium.

3. Memory Unit:
• Memory unit is an essential component of Digital
Computer. It is where all data intermediate and
find results are stored.
• The data read from the main storage or an input
unit are transferred to the computer’s
Memory where they are available for processing.
• This memory unit is used to hold the instructions
to be executed and data to be processes

System buses
• Bus is a communication channel.
• Characteristic of bus is shared transmission media.
• Limitation of a bus is only one transmission at a time.
• A bus which is used to provide the communication
between the major components
of a computer is called as System bus.

System bus contains 3 categories of lines used to
provide the communication between the CPU,
memory and IO Devices named as:
1. Address Bus ( AL )
2. Data Bus ( DL )
3. Control Bus ( CL )

1.Address Bus:
• Used to carry the address to memory ad IO
• Unidirectional
• Based on width of a address bus we can
determine the capacity of a main memory

2.Data Bus:
• Used to carry the binary data between the
CPU, memory and IO.
• Bidirectional
• Based on the width of a data bus we can
determine the word length of a CPU.
• Based on the word length we can
determine the performance of a CPU.

3.Control Bus:
• Used to carry the control signals and timing signals
• Control signals indicates type of operation.
• Timing Signals used to synchronize the memory and IO
operations with a CPU clock.

The CPU executes the instruction in series as
following:
• Fetching Instruction from memory into IR register
• Change the position of program counter
• Decode the instruction(Determine the type of
instruction)
• Execute the instruction
CPU Instruction Execution

Bus Organization for Seven CPU Registers

Example
• To perform the operation R3 = R1+R2 We have to
provide following binary selection variable to the
select inputs.
1. SEL A : 001 -To place the contents of R1 into bus A.
2. SEL B : 010 - to place the contents of R2 into bus B
3. SEL OPR : 10010 – to perform the arithmetic
addition A+B
4. SEL REG or SEL D : 011 –to place the result
available on output bus in R3.

Operation selection code Operation symbol
0000 Transfer A TSFA
0001 Increment A INCA
10010 A+B ADD
0011 A-B SUB
0100 Decrement A DECA
0101 A AND B AND
0110 A OR B OR
0111 A XOR B XOR
1000 Complement A COMA
1001 Shift right A SHRA
1010 Shift left A SHLA
Encoding of ALU Operations

What is Control Word?
• The combined value of a binary selection
inputs specifies the control word.
• It consist of four fields SELA,SELB,and SELD
or SELREG contains three bit each and SELOPR
field contains four bits thus the total bits in the
control word are 14-bits.
SEL A SELB SELREG OR
SELD
SELOPR

Flag Register
•The Flag register is a Special Purpose
Register.
•Depending upon the value of result after any
arithmetic and logical operation the flag bits
become set (1) or reset (0).
•Flag register is divided into two types
1. Status Flag.
2. Control Flag.

Status Flag Register
•Status Register is Hardware Register ,that contains
information about the state of processor.
•There are 6 flag registers in 8086 microprocessor
These flags are conditional/status flags.
1.Sign Flag (S)
2.Zero Flag (Z)
3.Auxiliary Carry Flag (AC)
4.Parity Flag (P)
5.Carry Flag (CY)
6.Overflow Flag (O)

1.Sign Flag (S/N):
•Indicates that the result of a mathematical
operation is negative.
2.Zero Flag (Z):
•Indicates that the result of an arithmetic or logical
operation was zero.
3.Auxiliary Carry Flag (AC)/ Half-Carry Flag (H)/
Digit Carry (DC)/ Digit Adjust Flag:
•This flag is used in BCD number system (0-9). This
is the only flag register which is not accessible by
the programmer.

4.Parity Flag (P):
•Indicates whether the number of set bits of the
last result is odd or even.
5.Carry Flag (CY)/ Borrow Flag:
•Carry is generated when performing n bit
operations and result is more than n bits, then flag
is set (1) otherwise it is reset (0).
6. Overflow Flag (O):
•This flag will be set (1) if the result of a signed
operation is too large to fit in the number of bits
available to represent it, otherwise reset (0).

Control Flag Register:
•The control flags enable or disable certain
operations of the microprocessor. There are 3
control flags in 8086 microprocessor and these
are:
1.Directional Flag (D):
•This flag is specifically used in string instructions.
•If directional flag is set (1), then access the string
data from higher memory location towards lower
memory location.
•If directional flag is reset (0), then access the
string data from lower memory location towards
higher memory location.

2.Interrupt Flag (I):
•This flag is for interrupts
•If interrupt flag is set (1), the microprocessor will
recognize interrupt requests from the peripherals.
•If interrupt flag is reset (0), the microprocessor will
not recognize any interrupt requests and will ignore
them
3.Trap Flag (T):
•This flag is used for on-chip debugging
•If trap flag is set (1), the CPU automatically generates
an internal interrupt after each instruction, allowing a
program to be inspected as it executes instruction by
instruction.
•If trap flag is reset (0), no function is performed.

ISA: Instruction Set Architecture
• Instruction set architecture(ISA) is the set of
processor design techniques used to implement the
instruction work flow on hardware.
• ISA tells you that how your processor going to process
your program instructions.

• There is no standard computer architecture accepting
different types like CISC, RISC, etc.

RISC Processor
•It is known as Reduced Instruction Set Computer.
•It is a type of microprocessor that has a limited
number of instructions.
•They can execute their instructions very fast
because instructions are very small and simple.
•RISC chips require fewer transistors which make
them cheaper to design and produce.

•In RISC, the instruction set contains simple and basic
instructions from which more complex instruction
can be produced.
•Most instructions complete in one cycle, which
allows the processor to handle many instructions at
same time.
•In this instructions are register based and data
transfer takes place from register to register.

Example of RISC
• Example : A = A * B;
• RISC processors only use simple instructions that can
be executed within one clock cycle.
• “MULT” command could be divided into three
separate commands:
1.“LOAD” which moves data from the memory
bank to a register
2. “PROD” which finds the product of two
operands located within the registers
3.“STORE” which moves data from a register
to the memory banks.

• In order to perform the exact series of steps described
in the CISC approach, a programmer would need to
code four lines of assembly:
LOAD R1, A
LOAD R2,B
PROD A, B
STORE R3, A
• At first, this may seem like a much less efficient way of
completing the operation. Because there are more
lines of code, more RAM is needed to store the
assembly level instructions.
• The compiler must also perform more work to convert
a high-level language statement into code of this form.

Advantage of RISC:-
• Each instruction requires only one clock cycle to
execute, the entire program will execute in
approximately the same amount of time as the multi-
cycle “MULT” command.
• These RISC “reduced instructions” require less
transistors of hardware space than the complex
instructions, leaving more room for general purpose
registers. Because all of the instructions execute in a
uniform amount of time (i.e. one clock)
• Pipelining is possible.

CISC Processor
• It is “COMPLEX INSTRUCTION SET”
• It was first developed by Intel.
• It contains large number of complex instructions.
• In this instructions are not register based.
• Instructions cannot be completed in one machine cycle.
• Data transfer is from memory to memory.
• Micro programmed control unit is found in CISC.
• Also they have variable instruction formats.

Example of CISC :
• Example: A = A * B;
• This is a C statement
• The primary goal of CISC architecture is to complete a
task in as few lines of assembly as possible.
• This is achieved by building processor hardware that
is capable of understanding & executing a series of
operations, this is where our CISC architecture
introduced .

• For this particular task, a CISC processor would come
prepared with a specific instruction (we’ll call it
“MULT”).
• When executed, this instruction Loads the two values
into separate registers Multiplies the operands in the
execution unit And finally third, stores the product in
the appropriate register.
• Thus, the entire task of multiplying two numbers can
be completed with one instruction:
• Assembly statement: MULT A,B

• MULT is what is known as a “complex instruction.”
• It operates directly on the computer’s memory banks
and does not require the programmer to explicitly call
any loading or storing functions.

Advantage of CISC:-
• Compiler has to do very little work to translate a
high-level language statement into assembly
• Length of the code is relatively short
• Very little RAM is required to store instructions
• The emphasis is put on building complex
instructions directly into the hardware.

Block Diagram of Control Unit:

Functions of Control Unit:
• Controls sequential instruction execution
• Interprets instructions
• Guides data flow through different computer areas
• Regulates and controls processor timing
• Sends and receives control signals from other
computer devices
• Handles multiple tasks, such as fetching, decoding,
execution handling and storing results

• The Hardwired Control organization involves the
control logic to be implemented with gates, flip-
flops, decoders, and other digital circuits
• A Hard-wired Control consists of two decoders, a
sequence counter, and a number of logic gates
• This organization can be very complicated if we
have to make the control unit large.

• Fixed logic circuits that correspond directly to
the Boolean expressions are used to generate
the control signals.
• Hardwired control is faster than micro-
programmed control.
• A controller that uses this approach can
operate at high speed.
• RISC architecture is based on hardwired
control unit

• The Micro programmed Control organization is
implemented by using the programming approach
• In Micro programmed Control, the micro-
operations are performed by executing a program
consisting of micro-instructions.
• The Control memory address register specifies the
address of the micro-instruction.
• The Control memory is assumed to be a ROM,
within which all control information is permanently
stored.
• The control register holds the microinstruction
fetched from the memory.

• The micro-instruction contains a control word
that specifies one or more micro-operations for
the data processor.
• While the micro-operations are being executed,
the next address is computed in the next address
generator circuit and then transferred into the
control address register to read the next
microinstruction.
• The next address generator is often referred to as
a micro-program sequencer, as it determines the
address sequence that is read from control
memory.

Difference between Hardwired Control and Micro
programmed Control
Hardwired Control Micro programmed Control
Technology is circuit based. Technology is software based.
It is implemented through flip-flops,
gates, decoders etc.
Microinstructions generate signals to
control the execution of instructions.
Fixed instruction format.
Variable instruction format (16-64 bits
per instruction).
Instructions are register based. Instructions are not register based.
ROM is not used. ROM is used.
It is used in RISC. It is used in CISC.
Faster decoding. Slower decoding.
Difficult to modify. Easily modified.
Chip area is less. Chip area is large

• Computer memory is any physical device capable of
storing information temporarily, like RAM (random
access memory), or permanently, like ROM (read-
only memory).
• Memory devices utilize integrated circuits and are
used by operating systems, software, and hardware.
•Below is an example of a 512 MB DIMM
computer memory module. This memory
module connects to the memory slot on a
computer motherboard.

Memory Access Methods
Each memory type, is a collection of numerous memory
locations. To access data from any memory, first it must
be located and then the data is read from the memory
location. Following are the methods to access
information from memory locations:
1. Random Access: Main memories are random access
memories, in which each memory location has a
unique address. Using this unique address any
memory location can be reached in the same
amount of time in any order.

2. Sequential Access: This methods allows memory
access in a sequence or in order.
3. Direct Access: In this mode, information is stored in
tracks, with each track having a separate read/write
head.

Cache Memory
• Cache is very fast and small memory that is placed
in between the CPU and the main memory.
• Cache memory can be accessed/is faster than RAM;
• It is used to hold common/expected/frequently
used data/operations;
• It is closer to CPU than RAM/situated between RAM
and CPU/on same board as CPU/ with faster
read/write speed;
• Cache memory is used to reduce the average
memory access times.

The steps to access the data from cache memory are:
• A request is made by the CPU
• Cache is checked for data
• If the data is found in the cache it is returned to the
CPU (this is called a cache hit)
• If the data is not found in the cache then the data will
be returned from the main memory.

Cache memory is fast and expensive. Traditionally, it is
categorized as "levels" that describe its closeness and
accessibility to the microprocessor. There are three general
cache levels:
• Level 1 or Register: is extremely fast but relatively small,
and is usually embedded in the processor chip as CPU
cache.
• Level 2 or Cache memory: is often more capacious than
L1. L2 cache may be embedded on the CPU, or it can be
on a separate chip or coprocessor and have a high-speed
alternative system bus connecting the cache and CPU.
That way it doesn't get slowed by traffic on the main
system bus.

• Level 3 or Main Memory: specialized memory
developed to improve the performance of L1 and L2.
L1 or L2 can be significantly faster than L3, though L3
is usually double the speed of DRAM. With multicore
processors each core can have dedicated L1 and L2
cache, but they can share an L3 cache. If an L3 cache
references an instruction, it is usually elevated to a
higher level of cache

Cache Performance
• When the processor needs to read or write a location in
main memory, it first checks for a corresponding entry
in the cache.
• If the processor finds that the memory location is in the
cache, a cache hit has occurred and data is read from
cache
• If the processor does not find the memory location in
the cache, a cache miss has occurred. For a cache miss,
the cache allocates a new entry and copies in data from
main memory, then the request is fulfilled from the
contents of the cache.

• The performance of cache memory is
frequently measured in terms of a quantity
called Hit ratio.
• Hit ratio = hits / (hits + misses)

Virtual Memory
• Virtual Memory is a storage scheme that provides user
an illusion of having a very big main memory. This is
done by treating a part of secondary memory as the
main memory.
• It is a technique that is implemented using both
hardware and software. It maps memory addresses
used by a program, called virtual addresses, into
physical addresses in computer memory.

• Less I/O required, leads to faster and easy swapping
of processes.
• More physical memory available, as programs are
stored on virtual memory, so they occupy very less
space on actual physical memory.
• Large programs can be written, as virtual space
available is huge compared to physical memory.
• It allows greater multiprogramming levels by using
less of the available (primary) memory for each
process.

Advantages of Virtual Memory
• The degree of Multiprogramming will be increased.
• User can run large application with less real RAM.
• There is no need to buy more memory RAMs.
Disadvantages of Virtual Memory
• The system becomes slower since swapping takes
time.
• It takes more time in switching between applications.
• The user will have the lesser hard disk space for its
use.

Virtual Memory Cache Memory
The term "virtual memory" refers to
space allocated on a hard disk where
data can be stored for fast access.
Cache memory is a small high-speed
memory usually Static RAM (SRAM) that
contains the most recently accessed
pieces of main memory.
Virtual memory enlarges the volume of
RAM.
By using cache Access time consumed by
the processor is less as compared to main
memory.
Operating system has the control over
virtual memory.
Hardware has the control over cache
memory.
The size of virtual memory is more than
cache memory.
The size of Cache memory is less than
virtual memory.
In virtual memory, larger programs can
be executed while there is a sufficiently
small amount of main memory.
The cache contains data items that are
most frequently used by the processor
while the whole program resides in the
secondary memory.
Difference between Virtual Memory and Cache Memory

Input / Output Bus and Interface Modules

• The I/O Subsystem of the computer, provides an
efficient mode of communication between the central
system and the outside environment
• Input Output Interface provides a method for
transferring information between internal storage and
external I/O devices.
• The purpose of communication link is to resolve the
differences that exist between the central computer
and each peripheral.
• Each Interface decodes the address and control
received from the I/O bus, interprets them for
peripherals and provides signals for the peripheral
controller
• It is also synchronizes the data flow and supervises the
transfer between peripheral and processor

Types of I/O Transfer Data:
The mode of transferring information between internal
storage to external I/O devices is known as I/O Interface
1. Programmed I/O or CPU initiated:
• Programmed I/O instructions are the result of I/O
instructions written in computer program. Each data
item transfer is initiated by the instruction in the
program.
• Usually the program controls data transfer to and
from CPU and peripheral. Transferring data under
programmed I/O requires constant monitoring of the
peripherals by the CPU

2. Interrupt Initiated I/O :
• In the programmed I/O method is time consuming
process because it keeps the processor busy
needlessly.
• This problem can be overcome by using interrupt
initiated I/O.
• In this when the interface determines that the
peripheral is ready for data transfer, it generates an
interrupt. After receiving the interrupt signal, the CPU
stops the task which it is processing and service the
I/O transfer and then returns back to its previous
processing task.

3. DMA (Direct Memory Access):
• Removing the CPU from the path and letting the peripheral
device manage the memory buses directly would improve
the speed of transfer. This technique is known as DMA.
• In this, the interface transfer data to and from the memory
through memory bus. A DMA controller manages to
transfer data between peripherals and memory unit
• Many hardware systems use DMA such as disk drive
controllers, graphic cards, network cards and sound cards
etc. It is also used for intra chip data transfer in multicore
processors.
• In DMA, CPU would initiate the transfer, do other
operations while the transfer is in progress and receive an
interrupt from the DMA controller when the transfer has
been completed

Parallel and Serial Communication
Parallel Transmission:
• In parallel communication the various data bits are
simultaneously transmitted using multiple
communication links between sender and receiver.

• This leads to a faster communication between the sender
and receiver.
• parallel communication is expensive.
• A large amount of data is being sent;
• The data being sent is time-sensitive;
• The data needs to be sent quickly
Advantages of Parallel Communication:
1.It is easier to Program.
2.It is faster than Serial Communication.
Disadvantages of Parallel Communication:
1. It is costly Method
2. Data bits can be out of sync, depending on transfer
distance and how fast each bit loads

Serial Transmission:
• In serial transmission, bits are sent sequentially on the
same channel (wire) which reduces costs for wire but
also slows the speed of transmission.
• Serial transmission can be either synchronous
or asynchronous

• In synchronous transmission, groups of bits are
combined into frames and frames are sent continuously
with or without data to be transmitted.
• In asynchronous transmission, groups of bits are sent as
independent units with start/stop flags and no data link
synchronization, to allow for arbitrary size gaps
between frames

Advantages of Serial Transmission:
• It uses less number of conducting wires, hence reduces
cost of the interface.
• It supports long distance data communication.
• It is easy to implement.
Disadvantages of Serial Transmission:
• slower speed of transmission
• This leads to wastage of bandwidth meant for data
transmission for useless stuff.

Computer Organization : CPU, Memory and I/O organization

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