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Digital Logic Design
1.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Digital Fundamentals Tenth Edition Floyd Chapter 6 © 2008 Pearson Education
2.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Basic rules of binary addition are performed by a half adder, which has two binary inputs (A and B) and two binary outputs (Carry out and Sum). Summary Half-Adder The inputs and outputs can be summarized on a truth table. Outputs Inputs A B Cout S 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 A B S Cout The logic symbol and equivalent circuit are: A B S Cout S
3.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Full-Adder By contrast, a full adder has three binary inputs (A, B, and Carry in) and two binary outputs (Carry out and Sum). The truth table summarizes the operation. Outputs Inputs A B Cout S Cin 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 A full-adder can be constructed from two half adders as shown: A B S Cout S A B S Cout S A B Sum Cout Cin A B S Cout S Cin Symbol
4.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Full-Adder A B S Cout S A B S Cout S For the given inputs, determine the intermediate and final outputs of the full adder. 1 1 0 1 0 The first half-adder has inputs of 1 and 0; therefore the Sum =1 and the Carry out = 0. The second half-adder has inputs of 1 and 1; therefore the Sum = 0 and the Carry out = 1. The OR gate has inputs of 1 and 0, therefore the final carry out = 1. 1 0 1 Sum Cout
5.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Full-Adder Outputs Inputs A B Cout S Cin 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 A B S Cout S A B S Cout S 1 1 0 1 0 1 0 1 Sum Cout Notice that the result from the previous example can be read directly on the truth table for a full adder.
6.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Parallel Adders Full adders are combined into parallel adders that can add binary numbers with multiple bits. A 4-bit adder is shown. A B S Cout Cin A B S Cout Cin A B S Cout Cin A B S Cout Cin A1 B1 S1 C0 S2 S3 S4 C1 C2 C3 C4 A2 B2 A3 B3 A4 B4 The output carry (C4) is not ready until it propagates through all of the full adders. This is called ripple carry, delaying the addition process.
7.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Parallel Adders The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder includes a carry in (labeled (C0) and a Carry out (labeled C4). The 74LS283 is an example. It features look-ahead carry, which adds logic to minimize the output carry delay. For the 74LS283, the maximum delay to the output carry is 17 ns. Binary number A Binary number B Input carry 4-bit sum Output carry 1 2 3 4 1 2 3 4 1 2 3 4 C0 C4 S
8.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Comparators The function of a comparator is to compare the magnitudes of two binary numbers to determine the relationship between them. In the simplest form, a comparator can test for equality using XNOR gates. How could you test two 4-bit numbers for equality? AND the outputs of four XNOR gates. A1 B1 A2 B2 A3 B3 A4 B4 Output
9.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Comparators IC comparators provide outputs to indicate which of the numbers is larger or if they are equal. The bits are numbered starting at 0, rather than 1 as in the case of adders. Cascading inputs are provided to expand the comparator to larger numbers. Outputs A1 A0 A2 A3 B1 B0 B2 B3 Cascading inputs COMP A = B A < B A > B A = B A < B A > B 0 0 3 3 A A The IC shown is the 4-bit 74LS85.
10.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Comparators IC comparators can be expanded using the cascading inputs as shown. The lowest order comparator has a HIGH on the A = B input. Outputs A1 A0 A2 A3 B1 B0 B2 B3 COMP A = B A < B A > B A = B A < B A > B 0 0 3 3 A A A5 A4 A6 A7 B5 B4 B6 B7 +5.0 V COMP A = B A < B A > B A = B A < B A > B 0 0 3 3 A A LSBs MSBs
11.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. Two simple decoders that detect the presence of the binary code 0011 are shown. The first has an active HIGH output; the second has an active LOW output. A1 A0 A2 A3 X Active HIGH decoder for 0011 A1 A0 A2 A3 X Active LOW decoder for 0011
12.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders A0 = 0 A1 = 1 A2 = 0 A3 = 1 1 Assume the output of the decoder shown is a logic 1. What are the inputs to the decoder?
13.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders IC decoders have multiple outputs to decode any combination of inputs. For example the binary-to-decimal decoder shown here has 16 outputs – one for each combination of binary inputs. Bin/Dec A0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4-bit binary input Decimal outputs A1 A2 A3 1 1 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 For the input shown, what is the output?
14.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders A specific integrated circuit decoder is the 74HC154 (shown as a 4-to-16 decoder). It includes two active LOW chip select lines which must be at the active level to enable the outputs. These lines can be used to expand the decoder to larger inputs. CS2 A1 A0 A2 A3 15 12 13 14 1 2 3 4 9 10 11 5 6 7 8 0 & 4 8 1 2 CS1 X/Y EN 74HC154
15.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders The 74LS138 is a 3-to-8 decoder with three chip select inputs (two active LOW, one active HIGH). In this Multisim circuit, the word generator (XWG1) is set up as an up counter. The logic analyzer (XLA1) compares the input and outputs of the decoder. Inputs are blue, outputs are red.
16.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders Inputs are blue, outputs are red. How will the waveforms change if the word generator is configured as a down counter instead of an up counter?
17.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders The chip select inputs can be used to expand a decoder. In this circuit, two 74LS138s are configured as a 16 line decoder. Notice how the MSB is connected to one active LOW and one active HIGH chip select. The next slide shows the logic analyzer output…
18.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders Is the word generator set as an up counter or a down counter? (The least significant decoder output at the top). It is an up counter.
19.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Decoders BCD-to-decimal decoders accept a binary coded decimal input and activate one of ten possible decimal digit indications. BCD/DEC 0 1 2 3 4 5 6 7 8 9 1 2 4 8 74HC42 (11) (10) (9) (7) (6) (5) (4) (3) (2) (1) (15) (14) (13) (12) A1 A0 A2 A3 Assume the inputs to the 74HC42 decoder are the sequence 0101, 0110, 0011, and 0010. Describe the output. All lines are HIGH except for one active output, which is LOW. The active outputs are 5, 6, 3, and 2 in that order.
20.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary BCD Decoder/Driver Another useful decoder is the 74LS47. This is a BCD-to- seven segment display with active LOW outputs. The a-g outputs are designed for much higher current than most devices (hence the word driver in the name). a b c d e f g 1 2 4 8 (16) (4) (13) (12) (11) (10) (9) (15) (14) (1) (2) (6) (7) (3) (5) (8) BCD inputs Outputs to seven segment device GND VCC BCD/7-seg BI/RBO BI/RBO LT RBI LT RBI 74LS47
21.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary BCD Decoder/Driver Here the 7447A is an connected to an LED seven segment display. Notice the current limiting resistors, required to prevent overdriving the LED display. VCC GND +5.0 V +5.0 V R's = 330 W a b c d e f g a b c d e f g MAN72 74LS47 LT BI/RBO RBI 1.0 kW 1 1 2 2 3,9,14 3 4 5 6 7 7 8 8 9 10 10 11 11 12 13 13 14 15 16 BCD/7-seg BCD input D C B A
22.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary BCD Decoder/Driver a b c d e f g BI/RBO 0 0 0 0 8 4 2 1 RBI LT 0 74LS47 a b c d e f g BI/RBO 0 0 0 0 8 4 2 1 RBI LT 0 74LS47 a b c d e f g BI/RBO 0 0 1 1 8 4 2 1 RBI LT 0 74LS47 a b c d e f g BI/RBO 0 0 0 0 8 4 2 1 RBI LT 1 74LS47 Blanked Blanked The 74LS47 features leading zero suppression, which blanks unnecessary leading zeros but keeps significant zeros as illustrated here. The BI/RBO output is connected to the RBI input of the next decoder. Depending on the display type, current limiting resistors may be required.
23.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary BCD Decoder/Driver Blanked Blanked a b c d e f g BI/RBO 0 1 0 1 8 4 2 1 RBI LT 74LS47 1 a b c d e f g BI/RBO 0 1 1 1 8 4 2 1 RBI LT 74LS47 a b c d e f g BI/RBO 0 0 0 0 8 4 2 1 RBI LT 74LS47 0 a b c d e f g BI/RBO 0 0 0 0 8 4 2 1 RBI LT 74LS47 0 Decimal point Trailing zero suppression blanks unnecessary trailing zeros to the right of the decimal point as illustrated here. The RBI input is connected to the BI/RBO output of the following decoder.
24.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Encoders An encoder accepts an active logic level on one of its inputs and converts it to a coded output, such as BCD or binary. The decimal to BCD is an encoder with an input for each of the ten decimal digits and four outputs that represent the BCD code for the active digit. The basic logic diagram is shown. There is no zero input because the outputs are all LOW when the input is zero. A1 A0 A2 A3 1 2 3 4 5 6 7 8 9
25.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Encoders A1 A0 A2 A3 Show how the decimal-to-BCD encoder converts the decimal number 3 into a BCD 0011. The top two OR gates have ones as indicated with the red lines. Thus the output is 0111. 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 0 0 1 0 0 1 1
26.
© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Encoders The 74HC147 is an example of an IC encoder. It is has ten active-LOW inputs and converts the active input to an active-LOW BCD output. This device is offers additional flexibility in that it is a priority encoder. This means that if more than one input is active, the one with the highest order decimal digit will be active. Decimal input BCD output 1 2 4 8 (16) (11) (12) (13) (1) (2) (4) (3) (5) (9) (7) (6) (14) (8) 1 2 3 4 5 6 7 8 (10) 9 GND VCC HPRI/BCD 74HC147 The next slide shows an application …
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© 2009 Pearson
Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Encoders VCC BCD complement of key press 1 2 3 4 5 6 7 8 9 1 2 4 8 9 8 7 6 5 3 2 1 0 4 R7 R8 R9 R4 R5 R6 R1 R2 R3 R0 Keyboard encoder HPRI/BCD 74HC147 The zero line is not needed by the encoder, but may be used by other circuits to detect a key press.
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Code converters There are various code converters that change one code to another. Two examples are the four bit binary-to-Gray converter and the Gray-to-binary converter. Show the conversion of binary 0111 to Gray and back. 0 0 0 1 1 1 Binary-to-Gray Gray-to-Binary MSB LSB MSB LSB 1 0 0 0 1 0 0 1 1 1
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed MUX 1 2 0 3 1 0 A multiplexer (MUX) selects one data line from two or more input lines and routes data from the selected line to the output. The particular data line that is selected is determined by the select inputs. Summary Multiplexers Two select lines are shown here to choose any of the four data inputs. Data select Data inputs Data output D1 D0 D2 D3 S1 S0 Which data line is selected if S1S0 = 10? D2 1 0
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed A demultiplexer (DEMUX) performs the opposite function from a MUX. It switches data from one input line to two or more data lines depending on the select inputs. The 74LS138 was introduced previously as a decoder but can also serve as a DEMUX. When connected as a DEMUX, data is applied to one of the enable inputs, and routed to the selected output line depending on the select variables. Note that the outputs are active-LOW as illustrated in the following example… Summary Demultiplexers 74LS138 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 DEMUX A A A 0 1 2 G G G 1 2A 2B Data select lines Enable inputs Data outputs
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Determine the outputs, given the inputs shown. Summary Demultiplexers 74LS138 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0 DEMUX A A A 0 1 2 G G G 1 2A 2B Data select lines Enable inputs Data outputs A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 A1 A2 G1 G2A G2B LOW LOW The output logic is opposite to the input because of the active-LOW convention. (Red shows the selected line).
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Parity Generators/Checkers Parity is an error detection method that uses an extra bit appended to a group of bits to force them to be either odd or even. In even parity, the total number of ones is even; in odd parity the total number of ones is odd. 11010011 S with odd parity = S with even parity = 01010011 The ASCII letter S is 1010011. Show the parity bit for the letter S with odd and even parity.
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Summary Parity Generators/Checkers The 74LS280 can be used to generate a parity bit or to check an incoming data stream for even or odd parity. Checker: The 74LS280 can test codes with up to 9 bits. The even output will normally be HIGH if the data lines have even parity; otherwise it will be LOW. Likewise, the odd output will normally be HIGH if the data lines have odd parity; otherwise it will be LOW. Generator: To generate even parity, the parity bit is taken from the odd parity output. To generate odd parity, the output is taken from the even parity output. (5) (6) (13) (1) (11) (12) (2) (10) (9) (8) F G D E H C B A (4) I 74LS280 Data inputs S Even S Odd
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Selected Key Terms Full-adder Cascading Ripple carry Look-ahead carry A digital circuit that adds two bits and an input carry bit to produce a sum and an output carry. Connecting two or more similar devices in a manner that expands the capability of one device. A method of binary addition in which the output carry from each adder becomes the input carry of the next higher order adder. A method of binary addition whereby carries from the preceding adder stages are anticipated, thus eliminating carry propagation delays.
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Selected Key Terms Decoder Encoder Priority encoder Multiplexer (MUX) Demultiplexer (DEMUX) A digital circuit that converts coded information into a familiar or noncoded form. A digital circuit that converts information into a coded form. An encoder in which only the highest value input digit is encoded and any other active input is ignored. A circuit that switches digital data from several input lines onto a single output line in a specified time sequence. A circuit that switches digital data from one input line onto a several output lines in a specified time sequence.
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 1. For the full-adder shown, assume the input bits are as shown with A = 0, B = 0, Cin = 1. The Sum and Cout will be a. Sum = 0 Cout = 0 b. Sum = 0 Cout = 1 c. Sum = 1 Cout = 0 d. Sum = 1 Cout = 1 © 2008 Pearson Education A B S Cout S A B S Cout S 0 1 0 Sum Cout
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 2. The output will be LOW if a. A < B b. A > B c. both a and b are correct d. A = B © 2008 Pearson Education A1 B1 A2 B2 A3 B3 A4 B4 Output
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 3. If you expand two 4-bit comparators to accept two 8-bit numbers, the output of the least significant comparator is a. equal to the final output b. connected to the cascading inputs of the most significant comparator c. connected to the output of the most significant comparator d. not used © 2008 Pearson Education
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 4. Assume you want to decode the binary number 0011 with an active-LOW decoder. The missing gate should be a. an AND gate b. an OR gate c. a NAND gate d. a NOR gate © 2008 Pearson Education A1 A0 A2 A3 X ?
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 5. Assume you want to decode the binary number 0011 with an active-HIGH decoder. The missing gate should be a. an AND gate b. an OR gate c. a NAND gate d. a NOR gate © 2008 Pearson Education A1 A0 A2 A3 X ?
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 6. The 74138 is a 3-to-8 decoder. Together, two of these ICs can be used to form one 4-to-16 decoder. To do this, connect a. one decoder to the LSBs of the input; the other decoder to the MSBs of the input b. all chip select lines to ground c. all chip select lines to their active levels d. one chip select line on each decoder to the input MSB © 2008 Pearson Education
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 7. The decimal-to-binary encoder shown does not have a zero input. This is because a. when zero is the input, all lines should be LOW b. zero is not important c. zero will produce illegal logic levels d. another encoder is used for zero © 2008 Pearson Education A1 A0 A2 A3 1 2 3 4 5 6 7 8 9
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 8. If the data select lines of the MUX are S1S0 = 11, the output will be a. LOW b. HIGH c. equal to D0 d. equal to D3 © 2008 Pearson Education MUX 1 2 0 3 1 0 Data select Data inputs Data output D1 D0 D2 D3 S1 S0
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 9. The 74138 decoder can also be used as a. an encoder b. a DEMUX c. a MUX d. none of the above © 2008 Pearson Education
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed 10. The 74LS280 can generate even or odd parity. It can also be used as a. an adder b. a parity tester c. a MUX d. an encoder © 2008 Pearson Education
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Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Answers: 1. c 2. c 3. b 4. c 5. a 6. d 7. a 8. d 9. b 10. b
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