Xilinx XC7Z020-Based Processor Module Combining the performance of two-core ARM® Cortex-A9 and the flexibility and programmability of 7th generation FPGA

1. AX-SoM-XC7Z020
Processor module
Your main resource for projects based on Xilinx Zynq XC7Z020

2. Full datasheet
Page 2 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
Document history
HISTORYHISTORYHISTORYHISTORY
VERSIONVERSIONVERSIONVERSION VERSIONVERSIONVERSIONVERSION VERSIONVERSIONVERSIONVERSION
1.0.0
4-sep-2012
17:26
First draft version
1.1.0
12-nov-2012
10:16
Pin tables added
1.2.0
06-feb-2012
09:16
Components and connectors locating added. Name of motherboard connectors
fixed.
1.3.0
15-feb-2012
09:16
Fixed issue in Pinout.

3. Full datasheet
Page 3 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1. General information
The module AX-SOM-XC7Z020 – is high performance, high integrated and compact
module with optimal price. This module - ideal solution for building such embedded
devices as: medical equipment, video equipment, industrial controllers (PLCs),
multimedia devices and others, where a lot of peripheral modules is used and high
performance requires.
For module ready next BSPs:
Embedded Linux
Windows Embedded Compact 7
eCOS 3.0
FreeRTOS

4. Full datasheet
Page 4 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.1. Short description
Xilinx Zynq XC7Z020:
o 667-, 733-, 800 MHz ARM® 2 x Cortex-A9 MPCore
o VFP and NEON® SIMD instructions support
o TrustZone® support
o 3 x Watchdog timers
o L1 32KB I-Cache/32KB D-Cache, 512KB L2 Cache
o Hardware encryption blocks (AES, SHA)
o 85K Logic Cells Artix-7 FPGA
o 2x AXI 32b Master, 2x AXI 32b Slave
o 4x AXI 64b/32b memory windows between FPGA and PS
o AXI 64b ACP
o DMA
Up to 8Gbit DDR3 RAM
Up to 8Gbit NAND Flash
Up to 64Mbit QSPI Flash
Network: 2 x EMAC/GMAC (10/100/1G) with IEEE 1588v2 support
2 x USB 2.0 High Speed OTG (480 Mbit/s)
2 x MMC/SD/SDIO
2 x CAN 2.0 A/B
2 x UART
2 x I2C
2 x SPI
2 x XADC (12b)
GPIO
33,333MHz main oscillator
Power supply range for module 3,0…5,5V
Possible to set various I/O bank voltage
Module dimensions 56mm x 50mm
Small board to board connectors with 0,6mm step (Hirose FX8-120S-SV)

5. Full datasheet
Page 5 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.1. Functional description
Fig. 1: Functional diagram of the module
XC7Z020
@ 800MHz
DC/DCs
QSPI
Flash
16 MB
NAND
Flash
256MB..1GB
DDR3
256MB..1GB
@ 533MHzConnectors
2 x Hirose2 x Hirose2 x Hirose2 x Hirose
FX8FX8FX8FX8----120S120S120S120S----SVSVSVSV
DDRC

6. Full datasheet
Page 6 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.1. Description of the functional blocks
1.1.1. Xilinx Zynq-7000 XC7Z020 platform
Used Xilinx Zynq XC7Z020 in CLG484 package as main SoC.
1.1.2. DDR3 memory
By default, is used DDR3 Samsung K4B1G1646G-BCH9, with 256MBytes size
(Can be expanded up to 1GByte).
Beginning of DDR3 – 0x0000 0000 (Depends on OCM configuration).
1.1.3. QSPI Flash memory
By default, is used QSPI Flash Flash memory Numonyx N25Q128A11B1241F with
16MBytes.
QSPI Flash memory connected to QSPI0 bus.
1.1.4. NAND Flash memory
By default, is used NAND Flash memory Samsung MT29F4G08ABBDAHC-IT:D,
with 512MBytes size (Can be expanded up to 1GByte).
Bus connected to NAND interface with 8-bit bus width.
Take care about MIO: QSPI and NAND are using some same pins.Take care about MIO: QSPI and NAND are using some same pins.Take care about MIO: QSPI and NAND are using some same pins.Take care about MIO: QSPI and NAND are using some same pins.
1.1.5. Power supply
For VCCINT and VCCPINT (1,0V) are used DC/DC Micrel MIC22705YML. For
VCCO_DDR and PS_DDR (1,5V) are used LDO Micrel MIC38300HYHL. For VCCAUX,
VCCPAUX, VCCBRAM, VCCO_0, RSVDVCC, VCCADC, VCCO_MIO0_500, QSPI Flash,
NAND Flash (1,8V) are used LDO Micrel MIC38300HYHL. For DDR3 VREF_DDR is used TI
TPS51200DRC. For power sequencing is used Analog Devices ADM1185ARMZ-1.
1.1.6. Boot mode for Xilinx Zynq-7000 XC7Z020
User can select next boot modes according EPP Technical reference manual and
using BOOT_DEV[2:1] pins:
BOOT_DEV[2:1] = 00000000 ---- JTAG bootJTAG bootJTAG bootJTAG boot (need set JTAG_INDEP to 0)
BOOT_DEV[2:1] = 01010101 ---- NAND bootNAND bootNAND bootNAND boot
BOOT_DEV[2:1] = 10101010 ---- QSPI bootQSPI bootQSPI bootQSPI boot
BOOT_DEV[2:1] = 11111111 ---- SD bootSD bootSD bootSD boot
“1” means connection to 1,8V and “0” means connection to GND.

7. Full datasheet
Page 7 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.2. Connector description
For connection with motherboard 2 x Hirose FX8-120P-SV connectors (with 0,6 mm
step) are used.
1.2.1. The physical location of the connectors
Fig. 2: Locating components on the front of the module
Xilinx
Zynq
DDR3
NAND QSPI
Flash
DC/DC
DDR3
««««DONEDONEDONEDONE»»»» LEDLEDLEDLED
««««nPORnPORnPORnPOR»»»» LEDLEDLEDLED
LDO
LDO

8. Full datasheet
Page 8 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
Fig. 3: Locating connectors on the rear of the module
1.2.2. Signal description on X1-X2 connectors
Please take care about supported I/O voltage when connecting to pins.
Pin type:
MIO_1.8V - PS Digital I/O with 1,8V levels;
MIO_S - PS Digital I/O with selected voltage levels;
FPGA I/O - PL I/O with selected voltage levels;
Analog - Analog I/O;
Power in - Power input line;
Power out - Power output line;
Ground - Ground;
- - Other.
X1 (MIO)
X2 (FPGA)
1
2 120
119
1
2
119
120

9. Full datasheet
Page 9 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.1.1.1. X1 connector (PS MIO)
Pin
number
Signal Name GPIO Type Processor’s ball Note
1 VCC_IN Power in
2 ZNQ_TDI H13
3 VCC_IN Power in
4 ZNQ_TDO G14
5 VCC_IN Power in
6 ZNQ_TMS G12
7 VCC_IN Power in
8 ZNQ_TCK G11
9 VCC_IN Power in
10 nPOR
11 VCC_IN Power in
12 VCCBATT G9
13 VCC_IN Power in
14 nSRST
15 VCC_IN Power in
16 VCC_1.8V
17 VCC_IN Power in
18 GND Ground
19 VCC_IN Power in
20 MIO[49] GPIO1_49 C14
21 VCC_IN Power in
22 MIO[22] GPIO0_22 A14
23 VCC_IN Power in
24 MIO[37] GPIO1_37 B14
25 VCC_IN Power in
26 MIO[26] GPIO0_26 A13
27 VCC_IN Power in
28 MIO[34] GPIO1_34 B12
29 VCC_IN Power in
30 MIO[28] GPIO0_28 A12
31 GND Ground
32 MIO[43] GPIO1_43 B11
33 GND Ground
34 MIO[30] GPIO0_30 A11
35 GND Ground
36 MIO[47] GPIO1_47 B10
37 GND Ground
38 MIO[45] GPIO1_45 B9
39 GND Ground
40 MIO[35] GPIO1_35 F14
41 GND Ground
42 MIO[40] GPIO1_40 E14
43 GND Ground
44 GND Ground
45 GND Ground
46 MIO[39] GPIO1_39 C13
47 GND Ground
48 MIO[50] GPIO1_50 D13
49 GND Ground
50 MIO[44] GPIO1_44 E13
51 GND Ground
52 MIO[38] GPIO1_38 F13
53 GND Ground
54 MIO[53] GPIO1_53 C12
55 VCCMIO_1
56 MIO[46] GPIO1_46 D12

10. Full datasheet
Page 10 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
57 VCCMIO_1
58 MIO[25] GPIO0_25 F12
59 VCCMIO_1
60 MIO[33] GPIO1_33 G13
61 GND Ground
62 MIO[23] GPIO0_23 E11
63 GND Ground
64 MIO[48] GPIO1_48 D11
65 GND Ground
66 MIO[19] GPIO0_19 E10
67 VCCMIO_1_INPUT Power in
68 MIO[21] GPIO0_21 F11
69 VCCMIO_1_INPUT Power in
70 GND Ground
71 VCCMIO_1_INPUT Power in
72 MIO[51] GPIO1_51 C10
73 GND Ground
74 MIO[52] GPIO1_52 D10
75 GND Ground
76 MIO[31] GPIO0_31 F9
77 GND Ground
78 MIO[27] GPIO0_27 D7
79 GND Ground
80 MIO[32] GPIO1_32 C7
81 GND Ground
82 MIO[36] GPIO1_36 A9
83 GND Ground
84 MIO[17] GPIO0_17 E9
85 GND Ground
86 MIO[41] GPIO1_41 C8
87 GND Ground
88 MIO[42] GPIO1_42 D8
89 GND Ground
90 MIO[29] GPIO0_29 E8
91 GND Ground
92 MIO[16] GPIO0_16 D6
93 GND Ground
94 MIO[20] GPIO0_20 A8
95 GND Ground
96 GND Ground
97 GND Ground
98 MIO[24] GPIO0_24 B7
99 GND Ground
100 MIO[18] GPIO0_18 A7
101 GND Ground
102 GND Ground
103 GND Ground
104 MIO_VREF F8
105 GND Ground
106 GND Ground
107 GND Ground
108 PLL_BYP GPIO0_6 Connected via 20kOm to
A4 ball of Zynq EPP
109 GND Ground
110 JTAG_INDEP GPIO0_2 Connected via 20kOm to
A2 ball of Zynq EPP
111 GND Ground
112 BOOT_DEV[2] GPIO0_5 Connected via 20kOm to
A3 ball of Zynq EPP
113 GND Ground
114 BOOT_DEV[1] GPIO0_4 Connected via 20kOm to
E4 ball of Zynq EPP
115 GND Ground

11. Full datasheet
Page 11 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
116 MIO1_1V8 GPIO0_8 Connected via 20kOm to
E5 ball of Zynq EPP
117 GND Ground
118 VCC_1.8V
119 GND Ground
120 GND Ground
1.1.1.2. X2 connector (FPGA)
Pin
number
Signal Name GPIO Type Processor’s ball Note
1 IO_0_13 R7
2 GND Ground
3 IO_L15N_T2_DQS_13 AB1
4 IO_L21N_T3_DQS_13 V4
5 IO_L15P_T2_DQS_13 AB2
6 IO_L21P_T3_DQS_13 V5
7 IO_L16N_T2_13 AB4
8 IO_L20P_T3_13 T4
9 IO_L16P_T2_13 AB5
10 IO_L20N_T3_13 U4
11 IO_L17N_T2_13 AB6
12 IO_L24N_T3_13 W5
13 IO_L17P_T2_13 AB7
14 IO_L24P_T3_13 W6
15 IO_L11N_T1_SRCC_13 AA8
16 IO_L18P_T2_13 Y4
17 IO_L11P_T1_SRCC_13 AA9
18 IO_L18N_T2_13 AA4
19 IO_L9N_T1_DQS_13 AB9
20 IO_L22N_T3_13 U5
21 IO_L9P_T1_DQS_13 AB10
22 IO_L22P_T3_13 U6
23 IO_L8P_T1_13 AA11
24 IO_L13N_T2_MRCC_13 Y5
25 IO_L8N_T1_13 AB11
26 IO_L13P_T2_MRCC_13 Y6
27 IO_L7P_T1_13 AA12
28 IO_L23N_T3_13 W7
29 IO_L7N_T1_13 AB12
30 IO_L23P_T3_13 V7
31 IO_L12P_T1_MRCC_13 Y9
32 IO_L14N_T2_SRCC_13 AA6
33 IO_L12N_T1_MRCC_13 Y8
34 IO_L14P_T2_SRCC_13 AA7
35 IO_L6N_T0_VREF_13 U9
36 IO_L2N_T0_13 W8
37 IO_L6P_T0_13 U10
38 IO_L2P_T0_13 V8
39 IO_L5N_T0_13 U11
40 IO_L19N_T3_VREF_13 T6
41 IO_L5P_T0_13 U12
42 IO_L19P_T3_13 R6
43 VCCIO_13
44 IO_L3N_T0_DQS_13 W10
45 VCCIO_13
46 IO_L3P_T0_DQS_13 W11
47 VCCIO_13
48 IO_L10N_T1_13 Y10
49 GND Ground
50 IO_L10P_T1_13 Y11
51 GND Ground

12. Full datasheet
Page 12 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
52 IO_25_13 U7
53 GND Ground
54 IO_L1N_T0_13 V9
55 VCCIO_13_INPUT Power in
56 IO_L1P_T0_13 V10
57 VCCIO_13_INPUT Power in
58 IO_L4N_T0_13 W12
59 VCCIO_13_INPUT Power in
60 IO_L4P_T0_13 V12
61 IO_0_35 H17
62 IO_25_35 H18
63 IO_L24P_T3_AD15P_35 H22
64 IO_L4P_T0_35 G15
65 IO_L24N_T3_AD15N_35 G22
66 IO_L4N_T0_35 G16
67 IO_L23P_T3_35 F21
68 IO_L6P_T0_35 G17
69 IO_L23N_T3_35 F22
70 IO_L6N_T0_VREF_35 F17
71 IO_L17P_T2_AD5P_35 E21
72 IO_L19P_T3_35 H19
73 IO_L17N_T2_AD5N_35 D21
74 IO_L19N_T3_VREF_35 H20
75 IO_L16P_T2_35 D22
76 IO_L22N_T3_AD7N_35 G21
77 IO_L16N_T2_35 C22
78 IO_L22P_T3_AD7P_35 G20
79 IO_L18N_T2_AD13N_35 B22
80 IO_L20P_T3_AD6P_35 G19
81 IO_L18P_T2_AD13P_35 B21
82 IO_L20N_T3_AD6N_35 F19
83 IO_L2N_T0_AD8N_35 D17
84 IO_L21N_T3_DQS_AD14N_35 E20
85 IO_L2P_T0_AD8P_35 D16
86 IO_L21P_T3_DQS_AD14P_35 E19
87 IO_L11P_T1_SRCC_35 C17
88 IO_L5N_T0_AD9N_35 E18
89 IO_L11N_T1_SRCC_35 C18
90 IO_L5P_T0_AD9P_35 F18
91 IO_L8N_T1_AD10N_35 B17
92 IO_L1P_T0_AD0P_35 F16
93 IO_L8P_T1_AD10P_35 B16
94 IO_L1N_T0_AD0N_35 E16
95 IO_L7P_T1_AD2P_35 C15
96 IO_L3P_T0_DQS_AD1P_35 E15
97 IO_L7N_T1_AD2N_35 B15
98 IO_L3N_T0_DQS_AD1N_35 D15
99 IO_L15N_T2_DQS_AD12N_35 A22
100 IO_L14P_T2_AD4P_SRCC_35 D20
101 IO_L15P_T2_DQS_AD12P_35 A21
102 IO_L14N_T2_AD4N_SRCC_35 C20
103 VCCIO_35
104 IO_L13N_T2_MRCC_35 B20
105 VCCIO_35
106 IO_L13P_T2_MRCC_35 B19
107 VCCIO_35
108 IO_L12N_T1_MRCC_35 C19
109 GND Ground
110 IO_L12P_T1_MRCC_35 D18
111 GND Ground
112 IO_L10N_T1_AD11N_35 A19
113 GND Ground
114 IO_L10P_T1_AD11P_35 A18

13. Full datasheet
Page 13 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
115 VCCIO_35_INPUT Power in
116 IO_L9N_T1_DQS_AD3N_35 A17
117 VCCIO_35_INPUT Power in
118 IO_L9P_T1_DQS_AD3P_35 A16
119 VCCIO_35_INPUT Power in
120 GND Ground

14. Full datasheet
Page 14 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.2. Mechanical Outline
Fig. 4: Mechanical outline (top view)

15. Full datasheet
Page 15 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
Fig. 5: Mechanical outline and Bottom Connectors (bottom view)
• DXF or STEP model on request

16. Full datasheet
Page 16 Full datasheet: Processor module based on Xilinx Zynq XC7Z020
1.3. Electrical specification
Parameter Min Normal Max Unit
Power supply,
VCC_IN
3,0 3,3 5,5 V
Power consumption TBD TBD TBD mA
Please note that the output of the 1.0 V regulator is limited to 4 A. Please use the Xilinx XPower
Analyzer to estimate the power consumption of your design.
1.4. Order code
AXAXAXAX----SoMSoMSoMSoM----XC7Z020CESXC7Z020CESXC7Z020CESXC7Z020CES----RxRxRxRx----NxNxNxNx----SSSS16161616----IIII
XC7Z020CES – Engineering sample;
XC7Z020 – Final version of Zynq SoC (now not accessible);
Rx – DDR3 RAM size, [256, 512, 1024] – example: 256 MBytes DDR3 RAM – R256;
Nx – NAND Flash size, [256, 512, 1024] – example: 256 MBytes NAND Flash – N256;
I – industrial temp range.
Order example:
AX-SoM-XC7Z020CES-R256-N256,
with this order code, on module will be installed next configuration: Xilinx XC7Z020CES, 256 MBytes
DDR3 RAM, 256 MBytes NAND Flash and without QSPI Flash. All components in commercial
temperature range.
By default, this module shipped with Embedded Linux OS.