Esd the broad impact and design challenges part2of2

Part II:
Challenges in the Design of
Integrated Circuits for ESD/EOS
Integrated Circuits for ESD/EOS
Robustness
Terry Welsher
©2011 ASQ & Presentation Terry
Presented live on Jul 07th, 2011

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Part II:
Challenges in the Design of Integrated Circuits
for ESD/EOS Robustness

Professional Services Only
No Product Sales!

•  Client Locations Terry Welsher
www.dangelmayer.com

Outline
•  Factory Control vs. Device Protection
•  ESD Threshold Roadmap Revisited
•  Industry Council on ESD Targets
•  Changes in Design Targets
•  2000 volts HBM
•  CDM Challenges
•  “Machine” Model
•  System Level Issues
•  EOS

p2
Copyright © 2011 Dangelmayer Associates

ESD Control and Protection

Control Protection

Range of
10000 Events
Occurring
Electrostatic Voltage

without Static
1000
Controls Device Sensitivity with
Protection Circuitry

100

Events with
Ordinary Class 0
Controls
10
Device Sensitivity
w/o protection circuits
Advanced Controls
MR Head Sensitivity


ESD Sensitivity Trends - Revisited

p4

ESDA Technology Roadmap
HBM Roadmap (Min-Max)
6kV

4kV

2kV

1kV
ESD Control Methods
0V
1978 1983 1988 1993 1998 2003 2008 2013

ESD Control is becoming increasingly critical!

p5

Typical IC With Protection Circuitry

Protection Circuits
Protection Circuits
Constrained or Omitted By:
• Technology Node Feature Sizes
• Circuit Functionality
Functional Circuitry
• I/O Density
• Circuit Speed Requirements


ESDA Technology Roadmap
CDM Roadmap (Min-Max)
1000V

750V

500V

250V

125V
ESD Control Methods
0V
1978 1983 1988 1993 1998 2003 2008 2013

ESD Control is becoming increasingly critical!

p7

Misuse of ESD Classifications
Classification Voltage Range (V)

0A < 125

0B 125 to < 250

1A 250 to < 500

1B 500 to < 1000

1C 1000 to < 2000

2 2000 to < 4000

3A 4000 to < 8000

3B ≥ 8000

There is no industry standard for tailoring control procedures
according to these levels


Industry Council on ESD Target
Levels
Mission

•  Review the ESD robustness requirements of modern IC products
to allow safe handling in an ESD protected area.

•  While accommodating both the capability of the manufacturing
sites and the constraints posed by downscaled process
technologies on practical protection designs, the Council
provides a consolidated recommendation for future ESD
target levels.

•  The Council Members and Associates promote these
recommended targets for adoption as company goals.

•  Being an independent entity, the Council presents the results and
supportive data to all interested standardization bodies.


Industry Council on ESD
Target Levels

11

Industry Council White Papers

•  White Paper 1: A Case for Lowering Component
Level HBM/MM ESD Specifications and
Requirements.
•  White Paper 2: A Case for Lowering Component
Level CDM ESD Specifications and Requirements
•  White Paper 3: System Level ESD
Part I: Common Misconceptions and
Recommended Basic Approaches


Challenge and Effort of Meeting ESD Level Requirements

Required Effort and Resources
HBM
2kV
n @
tai
ain
M
kV HBM
n @1
D esig
vel
Han dling Le
Meet Safe

Tech. Node 130nm 90nm 65nm 45nm 32nm 22nm
Qualification 2001 2003 2005 2008 2010 2014
Year
Reducing to 1kV will alleviate a lot of ESD effort but as technologies
are scaled down further the challenge will continue…
13
Copyright © 2011 Dangelmayer Associates Industry Council

Cost of ESD Control
The cost of ESD
Effort to Achieve High Yield

control does not
increase for 2kV
or 500V devices
Basic ESD Control

500V 1 kV 2 kV 16 kV
HBM Level

Where is the data?

Ø  ESD/EOS failures as
1 dpm line all devices
provided by various members
1 of the Industry Council
based on 21 billion devices
Ø  Includes both automotive
"EOS/ESD" fails per million devices

0,1 products and consumer ICs
Ø  A vast majority of the returns
are often found to be due to
0,01
with 1.5kV HBM
with 500V HBM

EOS
0.7 billion sold
4.8 billion sold

9.3 billion sold
5.7 billion sold
with 1kV HBM

witj 2kV HBM
1E-3
Ø  Total return rate due to EOS/
ESD fails < 1 dpm
Ø  No obvious correlation of
1E-4
EOS/ESD returns to HBM
500 1000 1500 2000
levels of 500 V … 2 kV
HBM robustness

This data represents products shipped at various ESD
levels with the same basic factory control Industry Council
15

Conclusion for HBM
•  2 kV HBM design is frequently causing
unnecessary qualification delays across
the technologies
•  HBM qualification levels between 500 V
and 2 kV exhibit the same level of
manufacturing quality and field
robustness
•  Targeting 1kV HBM is safe and is proven
to provide margin*
*AT&T used a 500 volt requirement starting in 1988 with no HBM
problems

November 2010 Industry Council 16

CBE vs. CDM Discharge
Waveform Comparison
FICBM vs. FICDM Discharge Waveforms
(250 V) Voltage
for DSP with a 250V Charge
10
GND test pad FICBM
Peak Current (Amps)

8
GND pin FICDM
6

4
2

0

-2
0.00

0.25

0.50

0.75

1.00

1.25

1.50
Time (nanoseconds)

Courtesy: Andrew Olney, Quality Director, Analog Devices


CDM Peak Current Dependence on Pin Count


CDM Threshold Dependencies
Larger Device Package Size

Higher
Operating
Speeds

p21
Copyright © 2011 Dangelmayer Associates Ref: Industry Council WPII 2009

Conclusions for CDM


Machine Model evolved from HBM

HBM MM
Simple Plug-In Module for Existing HBM Tester


MM Relation to HBM, CDM

Ø To avoid high charging voltages from the HBM test,
MM* was thought to be a good substitute with lower
pre-charging voltage but with equivalent current
stress.
Ø There was really no intention to address any
different failure mechanisms to HBM.
Ø In the vast majority of cases, analyses between HBM
and MM show the same damage sites
Ø This is in contrast to CDM, where the rise time is
much faster – often leading to voltage drops and
typically resulting in unique oxide failures

*It isn’t clear when the name “machine” was attached
to this model.
24

Failure Analysis on Same I/O Pin for Both HBM and MM
Stress
HBM 3.5kV MM 230V

Electrical signatures for
both HBM and MM
failures: Increase in
leakage;

Site of damage: ESD
Diode

MM Relation to HBM, CDM

Ø It was also wrongly assumed that it models the fast
discharge from or to a metal surface better than the
HBM test.
Ø Meanwhile, it is now known that fast discharges
are reproduced best by CDM.
Ø Field failures due to ESD are rare, and if any do
The root cause of almost all ESD failures of ICs is
occur they often can be correlated to weak CDM
either poor CDM design and poor CDM controls in
protection design or poor control of static charges
factories.
in manufacturing

26

JEDEC’s New Official Position on MM:

JESD22-A115C is a reference document; it is not a
requirement per JESD47G.

Machine Model as described in JESD22-A115C
should not be used as a requirement for IC ESD
Qualification.

Only HBM and CDM are the necessary ESD
Qualification test methods as specified in Stress
Test Driven Qualification of Integrated Circuits
(JESD47G).


Typical Set-Up: IEC 61000-4-2
System Level ESD

Metallic part

ESD tip
perpendicular
to EUT surface Wall Insulating
outlet foam

EUT
0,03 m ≥ 0,6 m

≥1m
0,1 m
insulating
support ESD
generator Ground
≥1m
GRP strap


ESD Testing
§  How does one test for ESD robustness?
•  Component ESD testing (i.e., HBM and CDM) of ICs is
intended to ensure that ICs survive the manufacturing
process inside ESD Protected Areas (EPA).
•  System level ESD testing is intended to ensure that
finished products can continue normal operation during
and after a system level ESD strike.
–  The IEC ESD Test Method is used to represent one particular
scenario of a charged human holding a metal object to
discharge. This is a common test method used to assess the
ESD robustness of the system
–  Other test standards(e.g., ISO10605, DO-160) are used
depending on the application

Copyright © 2011 Dangelmayer Associates Industry Council 2010

Industry Wide Problem
There is a prevailing misunderstanding
between IC Suppliers and System Level
Designers :

•  ESD test specification requirements of system vs. component
providers;
•  Understanding of the ESD failure / upset mechanisms and
contributions to those mechanisms, from system specific vs.
component specific constraints;
•  Lack of acknowledged responsibility between system
designers and component providers regarding proper system
level ESD protection for their respective end products.

OEMs are attempting to use component ESD information as an
indicator of system level performance!

Industry Council 2010

Component Vs. System Test Results – Poor
Correlation

Analysis of system failure case studies having both
HBM and IEC data indicates no correlation of HBM
failure voltage to IEC failure voltage.

Component ESD Versus System
ESD
•  HBM/CDM and IEC are completely different tests,
and thus there is a clear lack of correlation between
the two methods
• High levels of HBM performance do not ensure
that system ESD robustness can be achieved
•  In fact in some cases, a high level of HBM
performance can be a detrimental to optimum
design of system protection


Differentiation of Internal Vs. External Pins
Internal External

Printed
IC Circuit

connector
Board
Interchip

IC IC

IC

bus

•  Internal Pins and External Pins should meet minimum HBM and CDM levels
•  External Pins must be designed for proper system ESD protection
Copyright © 2011 Dangelmayer Associates Industry Council 2010

Designing for the Overall System

• The HBM and CDM levels are
important only for component
External handling
Clamps • System ESD protection design
involves an understanding of the
system

System-Efficient ESD Design (SEED) Concept

PCB With Components

IEC IC
External Component Response
Characterization linked to the IC clamp
Pin’s Transient Characteristics

External
TVS

• For an efficient system protection design, the IC pin breakdown
characteristics play a critical role
• With this type of understanding, effective IEC protection design can be
achieved for any IC pin that interfaces with the external world

SEED Concept Details
1.  IC Supplier provides Transmission Line Pulse (TLP) data on the Interface Pin
2.  Board Designer characterizes the Transient Voltage Pulse (TVP) to determine
the Residual Pulse Stress (RPS) data (Voltage Vs. Time)
3.  Board components are adjusted to balance the RPS data to the TLP data

PCB With Components IC
Residual TLP
Pulse Stress Information
IEC
clamp
Board External
Component Pin
Design
External
TVS


Electrical Overstress (EOS) and Safe Operating Area
(SOA)

ESD Area EOS Area

SOA

Current limit

Power limit

I

P
Voltage

limit

V

Time to failure
causing localized failures.
Over voltage tends to damage breakdown sites.
Over voltage tends to damage breakdown sites.
Over current tends to fuse interconnects.
age tends to damage fuse interconnects.
Over current tends to breakdown sites.
Over power tends to to fuse interconnects.
melt larger areas.
Over currenttends to melt larger areas.
Over power tends
EOS: Wide spreading melt larger areas. large areas of damage.
of heat resulting in
Over power spreading of heat resulting in large areas of damage.
EOS: Wide tends to 37
ESD: Heat does not disperse much causing localized failures.
EOS: Heat does not disperse Slide 37 causing localized of damage.
Wide spreading of heat much
resulting in large areas failures.
ESD:

Sources of EOS from Power

" High ground impedance (inductive coupling)
" Ground loops
" Improper power wiring
" DC voltage from tools in automated
equipment
" DC voltage from ungrounded floating metal
" Faulty soldering irons and power tools
" Faulty power adaptors
" Hot plug-in and faulty power sequencing
" Wirebonding
Copyright 2010, Dangelmayer Assoc. & Semitracks Inc. p38

EOS Control and Design
" Unlike ESD, formal EOS prevention,
monitoring and auditing systems are not
common in manufacturing
" Like ESD, EOS failures are often the result
of lack of awareness of the problem
" Like ESD, many stakeholders
n  Product design
n  Test and Production equipment design
n  Facility design and maintenance
n  Quality/process control
" Unlike ESD, no standard tests, no standard
design Copyright 2010, Dangelmayer Assoc. & Semitracks Inc. 39

Questions?
Contact information:
Ted Dangelmayer
Terry Welsher
978 282 8888
ted@dangelmayer.com
www.dangelmayer.com
ESD Training Event:
DA ESD Workshop July 26th , 27th and 28th
Cape Ann, Massachusetts


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