A Programmable VCO for DVB-H Application

A Programmable VCO
for DVB-H Application
Saralah Alizadeh Arand
In The Name Of ALLAH
1

Outline
 Oscillator Basics
 Phase-noise
 VCO
 Noise Sources in VCO
 Design procedure
 Layout & post layout
 Comparison
 Conclusion
Oscillator Basics
2
 Feedback Model
 Negative resistance Model

Oscillator Basics
 What is an Oscillator?
 A circuit that produces an output signal of a specific frequency
 Oscillator Models
 Feedback :
 Negative Resistance:
Oscillator Basics
3
OSC
Vdd
Vout
Vss
Vdd
A
G
Vin Vout
+
+
-RA RP
Active
Circuit
Resonator

Feedback Model
 Feedback Model:
 Positive Feedback
 Transfer Function:
 Oscillation Condition:
 barkhausen criterion:
 The energy in the feedback path is the same magnitude and phase
as the input
Oscillator Basics
A
G
Vin Vout
+
+
G . A = 1∠0°
𝑉𝑜𝑢𝑡
Vin
=
G
1 − G . A
4

Feedback Model…
 For Stable Oscillation:
 Barkhausen Criterion Is Not Enough
 A Frequency Selective Element
 E.g. A Tank Circuit
 An Amplitude Limitig Element
 Nonlinear Behavior Of Devices Like Transistor
Oscillator Basics
5
Vdd
G
Vin Vout
+
+

Negative Resistance Model
 Oscillator:
 Negative Resistance (Active Circuit)
 Resonator (e.g. Tank Circuit)
 For A Stable Oscillation
 𝑹𝑷 + (−𝑹𝑨) = 𝟎 ⇒ 𝑹𝑷 = 𝑹𝑨
 NMOS Oscillator:
 𝑹𝒏𝒆𝒈𝒂𝒕𝒊𝒗𝒆 = −
𝟐
𝑮𝒎
 Oscillation Criteria:
 𝑮𝒎𝑻𝑶𝑻𝑨𝑳
. 𝑹𝑷 = 𝟏
 For Start up
 𝑮𝒎𝑻𝑶𝑻𝑨𝑳. 𝑹𝑷 > 𝟏
Oscillator Basics
-RA RP
Active
Circuit
Resonator
6
Negative
Resistance
Tank Circuit
Vdd
Vdd

Outline
 VCO
 Comparison
 Conclusion
7
 Phase Noise basics
 Leeson Model
 Phase-noise
Phase-noise
 Hajimiri Model

Phase-noise Basics
 What is the definition of Phase-noise?
 Noise power level at a frequency offset from the 𝝎𝟎
 The power is measured relative to the carrier
 Unit: dBc/Hz
Phase-noise
8
𝜔0
𝑃𝑆
𝑃𝑆𝑆𝐵
𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦
∆𝜔
1 𝐻𝑧
ℒ𝑡𝑜𝑡𝑎𝑙 ∆𝜔 = 10 log
𝑃𝑠𝑖𝑑𝑒𝑏𝑎𝑛𝑑 𝜔0 + Δ𝜔, 1𝐻𝑧
𝑃𝑐𝑎𝑟𝑟𝑖𝑒𝑟

Phase-noise Basics…
 Why Is Phase-noise Important?
Phase-noise
9
IF Filter

Phase-noise Models
 Phase-noise Models:
 Linear-Time Invariant Model (Leeson Model)
 Linear-Time Variant Model (Hajimiri Model)
Phase-noise
10

Leeson Model
 Linear-Time Invariant Model (Leeson Model)
 Phase noise:
 F: Active Device Noise Factor
 K: Boltzmans Constant
 T: Temperature
 Po: Output Power
 𝝎𝟎: Oscillator Center Frequency
 QL: loaded resonator quality factor
 𝚫𝝎 : frequency offset from carrier
Phase-noise
11
∆𝜔1/ 3
L (∆𝜔)
𝜔0/2
slope = 3 (due to 1/f3
)
slope = 2 (due to 1/f2
)
Noise floor
ℒ 𝜔0, Δ𝜔 = 10 log
2𝐹𝑘𝑇
𝑃0
. 1 +
𝜔0
2 𝐿Δ𝜔
2
. 1 +
𝜔𝑐
Δ𝜔

Leeson Model …
 Derivation of Leeson’s Equation:
 Using Feedback Model
 Transfer Function is:
 Oscillation Condition:
 Without loss of generality:
 𝑭 𝒔 is set equal to 1
 𝑩 𝒔  A Transconductance and a Tank circuit
Phase-noise
12
+
+
B(s)
F(s) Y(s)
X(s)
𝐻 𝑠 =
𝑌 𝑠
𝑋 𝑠
=
𝐹 𝑠
1 − 𝐹 𝑠 . 𝐵 𝑠
𝐹 𝑠 . 𝐵 𝑠 = 1
G(s)
+
+
Y(s)
X(s)
RP

Leeson Model …
 The impedance of the tank Circuit
 If : ∆𝜔 ≪ 𝜔0
 Noise Power Spectral Density :
Phase-noise
13
G(s)
+
+
Y(s)
X(s)
RP
𝑍 𝜔0 + ∆𝜔 =
𝑅𝑃
1 + 𝑗2 𝐿
∆𝜔
𝜔0
𝐻 𝑗𝜔 =
1
1 −
𝐺𝑚𝑅𝑃
1 + 𝑗2 𝐿
∆𝜔
𝜔0
= 1 +
1
𝑗2 𝐿
∆𝜔
𝜔0
𝐻 𝑠 =
𝐹 𝑠
1 − 𝐹 𝑠 . 𝐵 𝑠
𝑅𝑃. Gm = 1
𝑆𝑌 ∆𝜔 = 𝑆𝑋 ∆𝜔 . 𝐻 𝑗𝜔 . 𝐻∗
(𝑗𝜔)
𝑆𝑋 ∆𝜔 = 4FkT . 1 +
𝜔𝑐
Δ𝜔
𝑆𝑌 ∆𝜔 = 4FkT . 1 +
𝜔𝑐
Δ𝜔
. 1 +
1
𝑗2 𝐿
∆𝜔
𝜔0
. 1 −
1
𝑗2 𝐿
∆𝜔
𝜔0
ℒ 𝜔0, Δ𝜔 = 10 log
2𝐹𝑘𝑇
𝑃0
. 1 +
𝜔0
2 𝐿Δ𝜔
2
. 1 +
𝜔𝑐
Δ𝜔
 Phase noise:

Hajimiri Model …
 Linear-Time Variant Model (Hajimiri Model)
 Time Variant Model
 ISF (Impulse Sensitivity Function) (𝛤)
 Dimensionless
 Frequency Independent
 Amplitude Independent
 Periodic in 2𝝅
Phase-noise
14
C
L
i(t)

Hajimiri Model …
 Excess Phase:
 ISF is periodic and expressible as a Fourier series:
Phase-noise
15
𝛥𝜙 = 𝛤 𝜔0𝜏 .
𝛥𝑞
𝑞𝑚𝑎𝑥
ℎ𝜙 𝑡, 𝜏 =
𝛤 𝜔0𝜏
𝑞𝑚𝑎𝑥
. 𝑢(𝑡 − 𝜏)
𝜙 𝑡 =
−∞
∞
ℎ𝜙 𝑡, 𝜏 . 𝑖 𝜏 𝑑𝜏 =
−∞
𝑡
Γ 𝜔0𝜏
𝑞max
. 𝑖 𝜏 𝑑𝜏
𝛤 𝜔0𝜏 = 𝑐0 +
𝑛=1
∞
𝑐𝑛. cos 𝑛𝜔0𝜏
𝜙 𝑡 =
1
𝑞max
𝑐0
−∞
𝑡
𝑖 𝜏 𝑑𝜏 +
𝑛=1
∞
𝑐𝑛.
−∞
𝑡
𝑖 𝜏 𝑑𝜏 cos 𝑛𝜔0𝜏 𝑑𝜏

Hajimiri Model …
 Conversion of circuit noise to Excess Phase and Phase noise
 For input Noise Current:
 Phase noise:
 Phase noise in 𝟏/𝒇𝟐
Region:
Phase-noise
16
𝑖 𝜏 = 𝐼𝑛 cos[(𝑛𝜔0 + ∆𝜔)𝑡] 𝜙 𝑡 ≅
𝐼𝑛𝐶𝑛 sin ∆𝜔 𝑡
2𝑞𝑚𝑎𝑥 . ∆𝜔
𝑣𝑜𝑢𝑡 = Cos 𝜔0𝑡 + 𝜙 𝑡 𝑃𝑆𝐵𝐶 ∆𝜔 ≅ 10 log
𝐼𝑛𝐶𝑛
4 𝑞𝑚𝑎𝑥 ∆𝜔
2
𝐿 ∆𝜔 = 10 log10
𝑖𝑛
2
∆ 𝑛=0
∞
𝑐𝑛
2
4 . 𝑞𝑚𝑎𝑥
2
∆𝜔2
𝑛=0
∞
𝑐𝑛
2
=
1
𝜋
0
2𝜋
Γ 𝑥 2
𝑑𝑥 = 2Γ𝑟𝑚𝑠
2
𝐿 ∆𝜔 = 10 𝑙𝑜𝑔
Γ𝑟𝑚𝑠
2
𝑞𝑚𝑎𝑥
2 .
𝑖𝑛
2 Δ
2. Δ𝜔2
L (∆𝜔)
Log(∆𝜔)
1/f2
Region

Hajimiri Model …
 Phase noise in 𝟏/𝒇𝟑
Region :
 Current noise in 1/f region:
 Current noise in 1/f region:
 Reducing c0 will reduce flicker noise upconvertion.
 𝟏/𝒇𝟑 Corner Frequency:
Phase-noise
17
𝑖𝑛
2
,1 𝑓 = 𝑖𝑛
2
.
𝜔1 𝑓
Δ𝜔
𝐿 ∆𝜔 = 10 𝑙𝑜𝑔
𝑐0
𝑞𝑚𝑎𝑥
2 .
𝑖𝑛
2
Δ
8. Δ𝜔2
𝜔1 𝑓
Δ𝜔
L (∆𝜔)
Log(∆𝜔)
1/f 2
Region
1/f 3
Region
𝜔1 𝑓3 = 𝜔1 𝑓
𝑐0
2Γ𝑟𝑚𝑠
2
2
≈ 𝜔1 𝑓.
1
2
𝑐0
𝑐1
2

Hajimiri Model …
 The noise sources in many oscillators cannot be well modeled as
stationary
 Noise currents are a function of bias currents
 Cyclostationary
 𝜶 𝒙 :
 A deterministic periodic function that describing the noise
amplitude modulation
 Can be derived from device noise characteristics and operating
point
Phase-noise
18
𝜞𝒆𝒇𝒇 𝒙 = 𝚪 𝒙 . 𝜶 𝒙

Outline
 Phase-noise
 Comparison
 Conclusion
19
 VCO Basics
 VCO Structures
 VCO
VCO

VCO Basics
 VCO?
 A Circuit with an input Vtune and a periodic oscillating output
 VCO in an RF Link:
VCO
20
VCO
Vdd
Vout
Vtune
Vss
𝑉𝑂𝑈𝑇 = 𝑉0 sin 𝜔𝑐𝑡 + 𝜙

VCO Basics…
 VCO Parameters:
 Tuning Range:
 VCO Gain:
 An Important parameter in PLL
VCO
21
𝑇𝑢𝑛𝑖𝑛𝑔 𝑅𝑎𝑛𝑔𝑒 =
𝑚𝑎𝑥 − 𝑚𝑖𝑛
𝑐𝑒𝑛𝑡𝑒𝑟
𝐾𝑉𝐶𝑂 =
𝑑
𝑑𝑉𝑡𝑢𝑛𝑒
Frequency
Tuning Volatge
fmax
fmin
fc
K
VCO
Tuning Volatge

VCO Structures
 VCO Structures:
 NMOS & PMOS Structures:
 CMOS Structures:
VCO
22
Vdd
Vdd
Vdd Vdd
Vdd

VCO Structures…
 NMOS Structures
 Due to the inductors to the supply:
 Swing is up to twice the power supply voltage on each node
 Signal maximization Phase noise minimization
 (a) has a differential structure:
 Smaller harmonic distortion
 More symmetrical waveform
 Lower flicker noise upconversion
 (b) has less sensitivity to supply noise
 (a) has less sensitivity to ground noise
VCO
23
Vdd
Vdd
(a) (b)

VCO Structures…
 PMOS Structures
 Same as NMOS structures but:
 PMOS is not as fast as NMOS
 For the same transconductance  PMOS width is larger
 PMOS has lower flicker noise
VCO
24
a b

VCO Structures…
 CMOS Structures
 Negative resistance is generated by NMOS and PMOS
 It enabling to half power consumption For the same negative
resistance
 Removing the current source Structure (c)
 Advantages:
 Signal swing is maximized
 Tail is an important noise source
 Disadvantages:
 Higher harmonic distortion
 Higher upconversion of flicker noise
 Higher power supply sensitivity
VCO
25
Vdd Vdd
Vdd
a b c

VCO Structures…
 ISFeff Calculation:
 𝜞 𝒙 − Approximation:
 𝜶 𝒙 − Approximation:
 Noise sources:
 Thermal
 Flicker:
VCO
26
Γeff 𝑥 = Γ 𝑥 . 𝛼 𝑥
Γ 𝑥 =
′
′2
+ ′′2
𝐼2 = 4kTλ gm gm ∝ 𝑉
𝑔𝑠 − 𝑉𝑇 𝛼𝑡ℎ 𝑡 =
𝐼2 𝑡
𝐼2
𝑚𝑎𝑥
=
𝑉
𝑔𝑠 𝑡 − 𝑉𝑇
𝑉
𝑔𝑠,𝑚𝑎𝑥 − 𝑉𝑇
𝑉
𝑛
2
(Δ ) =
𝐾 𝐼𝐷𝑆
Δ 𝐶𝑜𝑥𝐿𝑒𝑓𝑓
2 𝛼1/𝑓 𝑡 =
𝑉
𝑛
2
𝑉
𝑛,𝑚𝑎𝑥
2 =
𝐼𝐷𝑆 𝑡
𝐼𝐷𝑆,𝑚𝑎𝑥

VCO Structures…
 ISFeff Comparison
VCO
27
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-9
-1.5
-1
-0.5
0
0.5
1
1.5
NMF
ISF
ISFeff
Vdd
Vdd
 PMOS Structure:
 NMOS Structure:
 CMOS Structure:
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-9
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
NMF
ISF
ISFeff
Vdd
0 0.5 1 1.5 2 2.5
x 10
-9
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
NMF
ISF
ISFeff

VCO Structures…
 ISFeff Comparison
VCO
28
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-9
-1.5
-1
-0.5
0
0.5
1
1.5
NMF
ISF
ISFeff
Vdd
Vdd
0 0.2 0.4 0.6 0.8 1 1.2
x 10
-9
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
NMF
ISF
ISFeff
Vdd
0 0.5 1 1.5 2 2.5
x 10
-9
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
NMF
ISF
ISFeff

Outline
 Phase-noise
 VCO
 Comparison
 Conclusion
29
 Current Source Noise
 Cross Coupled Transistors Noise
Noise Sources in VCO

 Thermal Noise
 Flicker Noise
 Thermal Noise
 Flicker Noise
30
Vdd
Vtune

Current Source Noise
 Thermal Noise:
 Noise in 𝜔0 ⇒ Mixer ⇒ Low Frequency
 Suppressed By Tank
 Noise in 2𝜔0 ⇒ Mixer ⇒ 𝜔0
 PM Noise → Phase noise
 AM Noise
 Nonlinear Elements:
 Varactor
 Switches
 AM to PM
 → Phase noise
31
Vdd
Vtune
Switchi
ng at f0
Vdd
Vtune
AM-PM Convertion
Switchi
ng at f0
Switchi
ng at f0
Phase-noise
𝝎0
AM&PM
2𝝎0

Current Source Noise…
 Flicker Noise:
 𝑽𝒏
𝟐
=
𝑲
𝑪𝒐𝒙𝑾𝑳
.
𝟏
𝒇
 𝝎𝒎 ⇒ Mixer ⇒ 2 Side bande at 𝝎𝟎 ± 𝝎𝒎
 → Flicker Noise Upconversion
 AM Noise → Nonlinear Elements
 AM to PM
 → Phase noise
 L ↑→ Phase noise↓
32
Vdd
Vtune
𝝎𝒎
Vdd
Vtune
AM-PM Convertion
Switchi
ng at f0
Switchi
ng at f0
Phase-noise
𝝎𝒎
𝝎0 ±𝝎𝒎
AM

Current Source Noise…
 Current Source Noise (Hajimiri Approach)
 Tail Node Oscillation:
 𝟐𝝎𝟎
 ISF
 C1 = 0 ⇒ Noise At 𝝎𝟎 Has no Effect
 Low Frequency Noise & → Phase noise
 Noise At 𝟐𝝎𝟎 → Phase noise
33
Vdd
Vtune

Cross Coupled Transistors Noise
 Noise Sources:
 Cyclostationary
 Stationary Approach( Thermal Noise)
 In Most Sensitive Time
 At Zero Crossing of Output
 Thermal Noise:
 𝒊𝒄𝒄
𝟐
=
𝟏
𝟒
𝒊𝒏𝟏
𝟐
+ 𝒊𝒏𝟐
𝟐
+ 𝒊𝒑𝟏
𝟐
+ 𝒊𝒑𝟐
𝟐
=
𝟏
𝟐
𝒊𝒏
𝟐
+ 𝒊𝒑
𝟐
34
Vdd
Vtune
i1(t) i2(t)
i1(t)- i2(t)
2
r
r
2r
 ISF Calculation
 Cyclostationary Approach:

Cross Coupled Transistors Noise…
 Flicker Noise:
 A Low Frequency Noise
 A Low Impedance At Drain
 Short
 Switch Noise Is In Parallel With The Bias Noise
 Upconversion
 Via The Same Mechanism For Tail Flicker Noise
35
Vdd
Vtune
Low
Impedance
Vdd
Vtune
Switch
Flicker noise
Switch
Flicker noise

Outline
 Phase-noise
 VCO
 Comparison
 Conclusion
36
 Device Sizing
 Bias Noise Suppression
Design procedure
 Bias Current Optimization
 Frequency Tuning
 Noise Filtering
 New Noise Filtering
 Phase Noise Programing

Device sizing
 Device sizing:
 W/L?
 Starts up
 Compensation of Tank Losses
 For Stable Oscillation:
 For Symmetric Waveform:
Design procedure
37
Vdd
Vtune
M1
M2
M3
M4
Vdd
Vtune
Rin,n
Rin,p
Tank Circuit
M1
M2
M3
M4
Rin,n
Vdd
Rin,p
𝑅𝑛𝑒𝑔𝑎𝑡𝑖𝑣𝑒 = 𝑅𝑖𝑛𝑛
∥ 𝑅𝑖𝑛𝑝
= −
2
𝐺𝑚𝑛 + 𝐺𝑚𝑝
𝐺𝑚𝑇𝑂𝑇𝐴𝐿
. 𝑅𝑃 = 1 𝐺𝑚𝑇𝑂𝑇𝐴𝐿
. 𝑅𝑃 > 1
𝑔𝑚𝑛𝑚𝑜𝑠
= 𝑔𝑚𝑝𝑚𝑜𝑠
=
𝐾𝑛
′ 𝑊
𝑛𝐼𝐷
𝐿𝑛
=
𝐾𝑝
′
𝑊
𝑝𝐼𝐷
𝐿𝑝
=
4
3 𝑅𝑃

Device sizing
 Tank Circuit
 Inductor
 Varactor
 Design Issues:
 Frequency
 Quality Factor:
 Is dominated by IND Q
 Start up:
 Rp
Design procedure
38
Vtune
Tank Circuit
ω0 =
1
𝐿 𝐶
0
2
4
6
8
10
12
14
0.00E+00 5.00E+08 1.00E+09
Series
Resistance
Frequency
0
1
2
3
4
5
6
7
8
0.00E+00 5.00E+08 1.00E+09 1.50E+09 2.00E+09
Axis
Title
Axis Title
𝐺𝑚𝑇𝑂𝑇𝐴𝐿
. 𝑅𝑃 > 1

Device sizing
 Using PMOS as Tail:
 Set to 800 MHz
 I = 5mA
 Cadence Simulation
 Phase Noise:
 -120 dBc/Hz @ 1MHz
 Noise Sources Contributions:
 M6  Bias
 M5  Tail
 M1&M2 flicker noise
 Increase NMOS Length
Design procedure
39
M1
M2
M3
M4
M5
M6
Device Param Noise Contribution
%
M6 id 1.02E-12 69.57
M5 id 1.77E-13 12.09
M2 fn 4.98E-14 3.4
M1 fn 4.98E-14 3.4
M6 fn 4.61E-14 3.14
M2 id 2.81E-14 1.92
M1 id 2.81E-14 1.92
%
M6 id 8.98E-13 73.8
M5 id 1.53E-13 12.61
M6 fn 4.06E-14 3.34
M2 id 2.30E-14 1.89
M1 id 2.30E-14 1.89
M1 fn 1.26E-14 1.03
M2 fn 1.26E-14 1.03
L11 rn 8.38E-15 0.69
L11 rn 8.38E-15 0.69
M4 id 5.46E-15 0.45
M3 id 5.46E-15 0.45

Bias Noise Suppression
 M6  Bias
 Bias Noise Suppression
 Bypass Capacitor
 Noise Sources Contribution:
 -126.7dBc/Hz @1MHz
 6 dB Improvement
Design procedure
40
M1
M2
M3
M4
M5
M6
%
M6 id 8.98E-13 73.8
M5 id 1.53E-13 12.61
M6 fn 4.06E-14 3.34
M2 id 2.30E-14 1.89
M1 id 2.30E-14 1.89
M1 fn 1.26E-14 1.03
M2 fn 1.26E-14 1.03
L11 rn 8.38E-15 0.69
L11 rn 8.38E-15 0.69
M4 id 5.46E-15 0.45
M3 id 5.46E-15 0.45
M1
M2
M3
M4
M5
M6
%
M6 id 1.58E-13 43.11
M5 id 7.81E-14 21.35
M1 id 2.33E-14 6.38
M2 id 2.33E-14 6.38
M1 fn 1.28E-14 3.51
M2 fn 1.28E-14 3.51
L11 rn 8.42E-15 2.3
L11 rn 8.42E-15 2.3
M3 id 5.59E-15 1.53
M4 id 5.59E-15 1.53
 Phase noise:
 M5  Tail
 M1&M2  Thermal

Bias Current Optimization…
 VCO Operation Modes:
 Current Limited
 Voltage Limited
 Phase noise:
 Current Limited Mode:
 𝑉 =
4
𝜋
𝐼𝑏𝑖𝑎𝑠 . 𝑅𝑒𝑞
 Current ↑ ⇒ Voltage ↑ ,Noise power ↑
 ⇒ S/N ↑
 Voltage Limited Mode:
 𝑉 = 𝑉𝐷𝐷
 Current ↑ ⇒ Noise power ↑
 ⇒ S/N ↓
 Iopt = 6mA
Design procedure
41
 I = 5mA  6mA

Frequency Tuning
 DVB-H
 VHF-III ⇒ 170-230 MHz
 UHF-IV/V ⇒ 470-862 MHz
 L ⇒ 1.452-1.492 GHz
 ⇒ 400-930 MHz
 Tuning with Varactor:
 Large Varactor
 KVCO ↑
 AM to PM ↑
 Sensitivity ↑
Design procedure
42
VHF
III
100M 200M 500M
400M
300M 700M
600M 900M
800M 1G 1.2G 1.3G 1.4G
1.1G 1.5GHz
UHF-IV/V L
VHF
III
100M 200M 500M
400M
300M 700M
600M 900M
800M 1G 1.2G 1.3G 1.4G
1.1G 1.5GHz
UHF-IV/V L
Tank Circuit

Frequency Tuning…
 ⇒ 400-930 MHz
 Varactor Only
 Coarse Tuning & Fine Tuning
 Corse Tuning
 Capacitor Bank
 Fine Tuning
 Varactor
 Kvco ↓
 Sensitivity ↓
Design procedure
43
100M 200M 500M
400M
300M 700M
600M 900M
800M 1GHz
UHF-IV/V
Frequency
Tuning Volatge
c0
c1
D0
D1
D2
D3
Vtune
To VCO
c2
c3
0000
1111
1110
0001
0010
0011
.
.
.
.
.
.
c0 c1 c4
D0 D1 D2 D3 D4
c2 c3
c0
c1
c4
D0
D1
D2
D3
D4
c2
c3

Noise Filtering
 Noise Filtering
 Reduce Tail Noise
 Reduce NMOS Noise
 Tail noise Suppression
 Current Source Role:
 Vgs1 = -Vgs2
 Vgs2 ↑ ⇒ Vgs1 ↓ , M1: off , M2: Triode
 ro2 ↓ ⇒ Load Impedance ↓ ⇒ QTANK ↓
 ⇒Adding Tail
 Vgs2 ↑ ⇒ Vgs1 ↓ , M1: off , M2: Triode
 No signal current can flow through ro2
 ⇒ QTANK ↑
 Current Source
 A high impedance in series with Swithes
Design procedure
44
Vdd
Vtune
OFF Triode
Output Voltage
Load Impedance
Time
M1 M2
Vdd
Vtune
Output Voltage
Load Impedance
Time
Time
M1 M2
OFF Triode
%
M5 id 1.58E-13 43.11
M6 id 7.81E-14 21.35
M1 id 2.33E-14 6.38
M2 id 2.33E-14 6.38
M1 fn 1.28E-14 3.51
M2 fn 1.28E-14 3.51
L11 rn 8.42E-15 2.3
L11 rn 8.42E-15 2.3
M3 id 5.59E-15 1.53
M4 id 5.59E-15 1.53
M1
M2
M3
M4
M5
M6
Vdd
 Tail Noise
 NMOS Noise

Noise Filtering…
 Tail noise Suppression
 Tail thermal noise around 2𝝎𝟎 causes phase noise
 In any balanced circuit:
 Odd harmonics circulate in a differential path
 Even harmonics flow in a common-mode path
 ⇒ Current source need only provide high impedance to even harmonics
 High impedance is only required at 2𝝎𝟎
 ⇒ A Narrowband circuit
 → Suppress noise at 2𝝎𝟎
 A large capacitor
 Shorts noise frequencies around 2𝝎𝟎
 An inductor is inserted
 To raise the impedance
 Resonate at 2𝝎𝟎
 Our Structure with tail noise Suppression
Design procedure
45
Vdd Vdd
Vtune

Noise Filtering…
 NMOS Transistors noise suppression
 Inserting a High Impedance
 Resonate at 2𝝎𝟎
 Filter Design
 Center frequency:
 2 × 670𝑀𝐻𝑧 = 1.34𝐺𝐻𝑧
Design procedure
46
Vtune
Vtune
100M 200M 500M
400M
300M 700M
600M 900M
800M 1GHz
UHF-IV/V
670MHz
 Phase noise in 700MHz:
 -140.6 dBc/Hz @ 1MHz
 Noise Sources Contributions:
Device Param Noise Contribution%
I1.L1.r2 rn 9.75E-16 12.58
I1.L1.r1 rn 9.75E-16 12.58
M1 id 7.81E-16 10.08
M2 id 7.81E-16 10.07
M3 id 3.26E-16 4.21
M4 id 3.26E-16 4.21
L1.r2 rn 3.15E-16 4.06
L2.r1 rn 3.10E-16 4
L3.rs2 rn 2.12E-16 2.73
L3.rs1 rn 2.12E-16 2.73
M6 id 2.09E-16 2.7
M1.rb rn 1.71E-16 2.21
M2.rb rn 1.71E-16 2.21

New Noise Filtering…
 Phase noise in Other Frequencies:
 500MHz ⇒-136.2 dBc/Hz @ 1MHz
 700MHz ⇒-140.6 dBc/Hz @ 1MHz
 850MHz ⇒-137.1 dBc/Hz @ 1MHz
 Tuning The Filter
 Complicated
 Difficult
 Using Multiple Filtering Rather Than Tuning The Filter
 Simple
Design procedure
47
Vtune
100M 200M 500M
400M
300M 700M
600M 900M
800M 1GHz
UHF-IV/V
670MHz
1G
800M 1.4G
1.2G 1.8G
1.6G
c0 c1 c4
D0 D1 D2 D3 D4
c2 c3
c0
c1
c4
D0
D1
D2
D3
D4
c2
c3
D0 D1 D2 D3 D4
D0
D1
D2
D3
D4
Vtune
D0 … D4

 Multiple Filtering:
 Logic Unit:
Design procedure
48
100M 200M 500M
400M
300M 700M
600M 900M
800M 1GHz
UHF-IV/V
670MHz
1G
800M 1.4G
1.2G 1.8G
1.6G
c0 c1 c4
D0 D1 D2 D3 D4
c2 c3
c0
c1
c4
D0
D1
D2
D3
D4
c2
c3
f1 f2 f3 f4 f5
f1
f2
f3
f4
f5
D0 … D4
Logic
Unit
D2…D4
f0 … f4
Vtune
0000
1111
1110
Frequency
Tuning Volatge
0001
0010
0011
.
.
.
.
.
.
D
4
D
3
D
2
f1
f2
f3
f4
f5

 Multiple Filtering
 Phase Noise:
 500MHz ⇒-140.7 dBc/Hz @ 1MHz
 700MHz ⇒-140.6 dBc/Hz @ 1MHz
 850MHz ⇒-140.8 dBc/Hz @ 1MHz
Design procedure
49
c0 c1 c4
D0 D1 D2 D3 D4
c2 c3
c0
c1
c4
D0
D1
D2
D3
D4
c2
c3
f1 f2 f3 f4 f5
f1
f2
f3
f4
f5
D0 … D4
Logic
Unit
D2…D4
f0 … f4
Vtune

Phase Noise Programing
 Changing Bias Current
 ⇒ Will Change The Phase Noise
 When More Phase noise Is Tolerable
 We Can Reduce Tail Current
 Less Power Is Consumed
 4 Bit Is Used To Control The Current
 Phase noise v.s. Bias Current:
Design procedure
50
Bit4
Bit3
Bit2
Bit1
M5
M6
M7
M8
M9
M10
Power
Control Bits
Current
Consumption
(mA)
Simulation Phase-noise
(dBc/Hz @
1MHz)
Output
Amplitude
(v)
0000 6 schematic -140.9 1.341
0001 4.6 schematic -137.2 1.149
0010 3.75 schematic -136.4 .973
0100 2.73 schematic -135.6 .75
0111 2 schematic -133 .572
1010 1.5 schematic -131.2 .474
1111 1 schematic -129.6 .361

Output Buffer
 Output Buffer
 Open Drain Buffer
 Simple
 Off Chip Bias T
 C1 & C2 ⇒ Reduce VCO Output
Design procedure
51
R= 50 ohm
Bias T
C1
C2
VBias

Outline
 Phase-noise
 VCO
 Comparison
 Conclusion
52
 Layout
 Post Layout
Layout & post layout

Layout
 Layout:
53
D5 D4 D3
f1
f2
f3
f4
f5
c0 c1 c4
D0 D1 D2 D3 D4
c2 c3
c0
c1
c4
D0
D1
D2
D3
D4
c2
c3
f1
f2
f3
f4
f5
f1
f2
f3
f4
f5
Bit4
Bit3
Bit2
Bit1
M6
M7
M8
M9
M10
Vtune

Post Layout
 Start up:
 470MHz ⇒-140.7 dBc/Hz @ 1MHz
 650MHz ⇒-140.5 dBc/Hz @ 1MHz
 850MHz ⇒-140.6 dBc/Hz @ 1MHz
 Comparision:
54
 Phse noise:
Frequency
(MHz)
(dBc/Hz @ 1MHz)
470 Schematic -140.8
Post layout -140.7
Post layout -140.5
Post layout -140.6

Post Layout
 Phase noise v.s. Bias Current:
 700MHz
55
Power
Control Bits
Current
Consumption
(mA)
(dBc/Hz @
1MHz)
Output
Amplitude
(v)
0000 6 schematic -140.9 1.341
Post layout -140.5 1.337
0001 4.6 schematic -137.2 1.149
Post layout -136.9 1.147
0010 3.75 schematic -136.4 .973
Post layout -136 .97
0100 2.73 schematic -135.6 .75
Post layout -135.2 .747
0111 2 schematic -133 .572
1010 1.5 schematic -131.2 .474
1111 1 schematic -129.6 .361

Post Layout
 Coarse & Fine Tuning
56

Outline
 Phase-noise
 VCO
 Conclusion
57
Comparison
 Comparison

Comparison
 Comparison:
58
Comparison
Technology
Center
Frequency
(Hz)
Tuning
Percent
Power
(mW)
Phase-
noise
(dBc/Hz)
Offset
Frequency
(Hz)
FOM
[38] 0.18u cmos 1.8G 23% 5 -127.5 1M -185.6
[39] 0.18u cmos 1.8G 25% 34 -132 1M 181.8
[41] 0.18u cmos 975M 60% 5 -98 100k -170.8
[42] 0.18u cmos 1.8G 73% 4.8 -126 1M -184
[43] 0.18u cmos 1.34G 68% 9 -135.3 1M -187
This Work 0.18u cmos 670M 78% 10.8 -140.7 1M -187.5
𝑭𝑶𝑴 = 𝓛 𝒇𝒐𝒇𝒇𝒔𝒆𝒕 − 𝟐𝟎 𝒍𝒐𝒈
𝒇𝒐𝒔𝒄
𝒇𝒐𝒇𝒇𝒔𝒆𝒕
+ 𝟏𝟎 𝒍𝒐𝒈
𝑷𝒅𝒊𝒔𝒔
𝟏𝒎𝑾

Outline
 Phase-noise
 VCO
 Comparison
59
Conclusion
 Conclusion

Conclusion
 A Review of VCO
 Noise Sources → Phase Noise
 Noise Filtering
 Wide Band Noise Filtering
 Phase Noise Programing
 This VCO Is Not Fabricated
60
Conclusion

Thanks For Your Attention…
?

A Programmable VCO for DVB-H Application

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