Unit 3 Emotional Intelligence and Spiritual Intelligence.pdf
On using BS to improve the
1. Tallinn Technical University :: May 4th 2009 This presentation is available at http://www.slideshare.net/josemmf Tallinn Technical University :: May 5th 2009 This presentation is available at http://www.slideshare.net/josemmf On using BS to improve the reliability and availability of reconfigurable hardware J. M. Martins Ferreira [ jmf@fe.up.pt ] FEUP / DEEC - Rua Dr. Roberto Frias 4200-537 Porto - PORTUGAL M. G. Gericota, G. R. Alves, M. Silva, J. M. Ferreira, “Reliability and Avaliability in Reconfigurable Computing: A Basis for a Common Solution,” IEEE Transactions on VLSI Systems , Vol. 16, No. 11, pp. 1545-1558 , Nov. 2008.
13. Replication flow: Time & space needed 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 22,444 26 094 Total 3,438 3 986 Disconnect the original CLB inputs 1,146 1 333 Disconnect the original CLB outputs 3,550 4 129 Place the CLB outputs in parallel 1,906 2 217 Disconnect all the auxiliary relocation circuit signals 1,844 2 145 Connect the clock enable inputs of both CLBs 0,238 277 BY_C=0 0,238 277 CC=0 0,379 441 BY_C=1 & CC=1 9,705 11 289 Copy the internal logic functionality and place the input signals in parallel Time (ms) No. of bytes Steps
23. Fault detection latency 34,820 40500 Total 15,813 18392 Disconnect the original CLB inputs and setup test configuration 1,146 1333 Disconnect the original CLB outputs 3,550 4129 Place the CLB outputs in parallel 1,906 2217 Disconnect all the auxiliary relocation circuit signals 1,844 2145 Connect the clock enable inputs of both CLBs 0,238 277 BY_C=0 0,238 277 CC=0 0,379 441 BY_C=1 CC=1 9,705 11 289 Copy logic f unctionality and parallel input signals Time (ms) 20MHz TCK # of bytes Synchronous circuits with clock enable [With the replication aid circuit ] 30,625 35621 Total 15,813 18392 Disconnect of the original CLB inputs and setup test configuration 0,923 1073 Disconnect of the original CLB outputs 3,433 3993 Place of the CLB outputs in parallel 10,457 12163 Copy of the internal logic functionality and place of the input signals in parallel Time (ms) 20MHz TCK # of bytes Synchronous circuits with free-running clock and combinational circuits [Without the replication aid circuit]
24. Worst-case fault detection latency (XCV200) The mean time to test the full CLB matrix is also the worst-case fault detection latency 4,726 5 497 Total 0,440 512 6 th 0,527 613 5 th 0,545 634 4 th 0,536 623 3 rd 2,678 3 115 2 nd Time (ms) 20MHz TCK # of bytes # of configurations File size and reconfiguration time of the test configurations 0,066 520 13 40 Time (ms) 20MHz TCK Total (bits) Length (bits) # of test vectors Shifting time for test vector application 4,088 40 1 022 Time (ms) 20MHz TCK # of test vectors # of cells of the BS register in a XCV200 Shifting time for the test vector responses from a CLB under test 26 472,235 ms @ TCK = 33 MHz 43 679,188 ms @ TCK = 20 MHz Occupation type: 25% synchronous, 50% combinational, 25% empty Mean time for the test of a 1176 CLBs matrix
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32. Tallinn Technical University :: May 4th 2009 This presentation is available at http://www.slideshare.net/josemmf Tallinn Technical University :: May 5th 2009 This presentation is available at http://www.slideshare.net/josemmf On using BS to improve the reliability and availability of reconfigurable hardware Thanks for your attention! J. M. Martins Ferreira [ jmf@fe.up.pt ]