Presentation covers: Low Voltage Differential Signalling (LVDS) - Why LVDS is so popular - How LVDS works - Pushing the envelope Essential PCB Routing Considerations - Designing for low-cost manufacture - Limitations of hardware compensation - Benefits of routing tuning - Propagation modes Basics of S-Parameters - Time domain/frequency domain conflicts in simulation - Transforming frequency-domain models for time-domain simulation Simulation - When simulation is essential - Putting it together

1. Gigabit LVDS Signalling on a PCB
assisted by Simulation and
S-Parameter Modelling
John Berrie
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2. Topics
• Low Voltage Differential Signalling (LVDS)
– Why LVDS is so popular
– How LVDS works
– Pushing the envelope
• Essential PCB Routing Considerations
– Designing for low-cost manufacture
‒ Limitations of hardware compensation
‒ Benefits of routing tuning
– Propagation modes
• Basics of S-Parameters
– Time domain/frequency domain conflicts in simulation
– Transforming frequency-domain models for time-domain simulation
• Simulation
– When simulation is essential
– Putting it together
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3. Why LVDS is so Popular
• Common-mode noise rejection
• Low voltage
• Low power
• Low noise emissions and susceptibility
• Compatible with gigabit speeds
• High availability of standard parts
– PCI Express
– FPGA
– HyperTransport
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4. Current-Mode Drivers
3.5mA
100Ω
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5. Simplex
RDIFF
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6. Dual Simplex
Rt
PCI Express Lane
Rt
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7. PCI Express Features
• Introduced by Intel in 2004
• High-speed serial bus replacement for PCI, PCI-X, AGP
– Software-compatible with PCI
• Point-to-point differential, dual simplex
• One dual simplex (two differential pairs) equal one lane
• Capacity per lane
– Version 1.x, 1.25GHz, 250MB/s
– Version 2.0, 2.5GHz, 500MB/s
– Version 3.0, 4GHz, 1GB/s
– Largest common lane count is 16 per bus
• Data transmitted in packets
– 8B/10B encoding balances ones and zeros
– Clock embedded within data
‒ Major implications for PCB routing
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8. Skew Matching in PCI Express
• Most critical
– Within each differential pair
‒ Align within a unit interval (one clock period)
• And then ...
– Within each 2-differential-pair dual simplex lane
‒ Desirable to make bidirectional operating speed more consistent
• And then ...
– From lane to lane
‒ Depends on minimum packet size
‒ Align within (bits in packet) unit intervals
‒ e.g. 128-bit packet means align within 128 unit intervals
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9. HyperTransport Features
• Dual simplex point-to-point
• 200MHz to 3.2GHz
• 32-bit full-speed up to 51.2GB/s
• Packet-based
• Separate clock and data
• Point-to-point dual simplex routing with Tunnel devices to create
daisy chains, stars and other topologies
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10. Important PCB Routing Considerations for
HyperTransport
• Data and commands are combined and transmitted in packets
• Clock and control are separate from data
– Clock to data skew constraints are required
• 2, 4, 8, 16 or 32 bit data path
• Designed to work on low-cost FR-4, including 4-layer boards
• On-die bridge termination
• Maximum route length up to around 0.75 metres, depending on
layer stack
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11. HyperTransport 3.1 Signal Groups in one
Link
• All differential pairs
• One CLK line per <=8
CAD lines CLK=Clock [m:0]
• One CTL line per <=8
CTL=Control[n:0]
CAD lines (Gen3)
• Skew constraints CAD=Command/Addr/Data[p:0]
between CAD, CTL and
CLK
CLK= Clock [m:0]
CTL=Control[n:0] Low-speed
signals PWROK
CAD=Command/Addr/Data[p:0] and RESET#
omitted from
this diagram
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12. Hardware Compensation
• Pre-emphasis
– Boost relative high frequency content (considering frequency domain)
‒ Higher-frequency content related to rise time and amplitude
– Stronger state change (considering time domain)
– Compensates for Inter-Symbol Interference (ISI) during rapid state changes
• Timing
– Simplifying required route topology
• Impedance
– Adapt to detected PCB electrical characteristics (characteristic impedance)
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13. Differential Pair Essentials
• Symmetry is key
Signal Vias and
Connector Series AC Ground Stitching
Pads (driven Coupling Vias Component
end) Capacitors Pads (receiving
end)
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14. Differential Pair Essentials
• Avoid significant en-route discontinuities and imbalance
– Simulate to check consequences of small discontinuities
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15. Uniformity = Predictability
• Design to avoid subtle
glitch culprits
– Environmental factors
– Undetected manufacturing
tolerance violations
• Design from the front end a
b
–
a
Tune to exceed b
performance a
‒ Improves re-usability
• Keep coupling uniform
– Predictable performance from the start
– Avoids simulator stress
– Electrically-equivalent PCB layers
– Uniform differential spacing
– Uniform pair-to-pair spacing and parallelism
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16. Desirable Field Lines in Differential Pairs
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17. Propagation Modes
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18. S-Parameters
• Useful for modelling high-speed passive components such as
filters and connectors
• Black box modelling technique
– Can be derived from hardware with no need to understand internal
behaviour
• Unlimited in frequency
• Each entry relates to a single frequency
– Large set of entries needed to cover component frequencies of a digital
signal
• Each entry describes how a wave of a single frequency arriving at
a single port is transformed in terms of relative amplitude and
phase as it is scattered to the other ports
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19. S-Parameters
• Scattering of wave arriving at Port 1 (reverse for arrival at Port 2)
Zo Zo
Port 1 Port 2
a1 b1 b2
=S11a1 =S21a1
• Scattering matrix for wave arriving at Port 1 or Port 2
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20. S-Parameter Model of Transmission Line
b2 V2 0.293 135
V0 50Ω V1 100Ω V2 S 21 S 12
a1
2
V0
2
0.707 0
0.828 135 0.585 j 0.585
b1 V1 0.467
S 11 S 22 2 1 2 1 0 0.321 0 0.321 j 0.000
200mm a1 VO 0.707
50Ω
V0=1V peak=0.707V RMS
V1=0.66
V peak=0.467V RMS
V2=0.414V peak=0.293V
RMS,
135 phase shift with
respect to V0
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21. Touchstone® File Format for S-Parameters
!2-Port S-parameters for 100Ω lossless transmission line with two
frequency points in Magnitude/Angle format
Frequency Units Parameters Type
Magnitude/Angle Normalize to 50Ω
Source/Load
# MHz S MA R 50
200.000 0.321 0.000 0.828 238.000 0.828 135.000 0.321 0.000
250.000 0.321 0.000 0.828 135.000 0.828 135.000 0.321 0.000
Frequency S11 S21 S12 S22
Alternative formats are DB (dB-angle) and RI (real-imaginary)
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22. Passive Component Modelling
• S-Parameter Model • Passive Network Model
– Black box model so no – Extrapolates and interpolates
assumptions automatically
– Valid only under tested – May lose validity at higher
conditions frequency
– Need to cover entire expected – Only models what is included
frequency range – Frequency or time domain
– Frequency domain
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23. Differential Channel with Common-Mode
Filter: S-Parameter or Obfuscated Passive
Network Model
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24. Simulation with Model Choices:
S-Parameter or Obfuscated Passive
Network Model
IBIS buffer model +
S-Parameter driver
model simulation
HSPICE transistor-
level Model +
obfuscated passive
model simulation
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25. Combined-Function Passive Devices
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26. Conclusion
• Point-to-point differential signalling is common and increasingly
standardised
• Ultra-fast data with low power being used whether needed or not
– Compare DDR2/DDR3 memory
• Cheapness of manufacture has been considered
– Adaptive signalling techniques
– Simplified topology
– Tolerance of PCB electrical characteristic variations
• But…
– For high-volume/cost-reduced, non-standard or safety-critical designs,
simulation is still essential
‒ And it's still advisable in all cases, even when following design rules
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27. The Partner for Success
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