Design of silicon photonic interconnect i cs in 65 nm cmos technology

CONTACT: PRAVEEN KUMAR. L (,+91 – 9791938249)
MAIL ID: sunsid1989@gmail.com, praveen@nexgenproject.com
Web: www.nexgenproject.com, www.finalyear-ieeeprojects.com
Design of Silicon Photonic Interconnect ICs in 65-nm
CMOS Technology
Abstract:
This paper describes a design methodology for CMOS silicon photonic interconnect ICs
according to CMOS technology scaling. As the CMOS process is scaled, the endurable voltage
stress and the intrinsic gain of the CMOS devices are reduced; therefore, a design of the high
swing transmitter and high-gain receiver required at the silicon photonic interface becomes much
more challenging. In this paper, a triple-stacked Mach–Zehnder modulator driver and an
inverter-based trans-impedance amplifier with inductive feedback are proposed, and the
robustness of the proposed designs is verified through Monte Carlo analyses. The prototype ICs
are fabricated using a 65-nm CMOS technology. The transmitter exhibits a 6 Vpp output swing,
98-mW power consumption, and 0.04-mm2 active area at 10 Gb/s. The receiver was verified
with a commercial photo detector, and it exhibits a 78-dB gain, 25.3-mW power consumption,
and 0.18-mm2 active area at 20 Gb/s. The proposed architecture of this paper the area and power
consumption are analysis using tanner tools.
Enhancement of the project:
Change the nanometer technology and parameters
Existing System:
The block diagram of the silicon photonic interconnects incorporating an MZ modulator and a
photodetector is shown in Fig. 1. The input data stream is serialized into the modulator driver,
and the driver output signal is delivered to the MZ modulator across the bond wire. The
continuous wave is modulated through the MZ modulator according to the input bit stream, and
the modulated optical signal propagates to the receiver side through the optical waveguide. The
received signal is radiated to the PD through a holographic lens; then, the PD converts the
photonic signal into a current. At the electrical IC front end, a transimpedance amplifier (TIA)
amplifies the input current signal and converts the signal from a current to a voltage. Finally, the
clock and data recovery circuit recovers the bit stream from the amplified signal. Because the
MZ modulator and the PD are used for an electron/photon conversion in this architecture, the
front-end circuits that directly interact with them—the output driver at the transmitter and the

TIA at the receiver—are the most critical building blocks in the silicon photonic transceiver IC.
The most critical issues that make the silicon photonic interconnect viable are the improved
energy efficiency and cost competitiveness compared with the conventional electrical
interconnect. The 2013 iNEMI roadmap suggested that the energy efficiency and I/O cost of the
optical interconnect will reach 1 pJ/bit and 0.23 $/Gb/s, respectively. Advanced CMOS
technology that offers low power consumption, high circuit function density, and low cost could
provide the best solution. Moreover, the silicon photonic interface should be integrated with
high-density CMOS logic blocks to realize the true silicon photonics. To utilize the advantages
of advanced CMOS technology, the silicon photonic interconnect should be compatible with a
scaled CMOS technology. However, there are two main design challenges for the CMOS silicon
photonic interface IC to accommodate the photonic devices. The first one is caused by the low
supply voltage used in advanced CMOS technology.

Fig. 1. Block diagram of the silicon photonic transceiver
Disadvantages:
 Low energy efficiency
Proposed System:
The photonic and electrical chips in the silicon photonic interconnect are not connected through
transmission lines but relatively short bond wires, as shown in Fig. 1. Therefore, the modulator
driver does not need to offer impedance matching, and it drives a capacitive load instead of a
resistive load, unlike conventional electrical links or long-reach optical links. Moreover, the MZ
modulator requires a drive signal with a high-voltage swing that exceeds the nominal supply
voltage of advanced CMOS technology, as mentioned previously. As a result, the modulator
driver in the silicon photonic transmitter IC must offer a sufficiently high-voltage swing across
the capacitive load.

Fig. 2. Circuit diagram of the proposed high-swing MZ modulator driver
We describe a 6 Vpp differential MZ modulator driver implemented using a 65-nm standard
CMOS technology. Fig. 2 shows the circuit diagram of the proposed driver. τh, τm, and τl denote
the buffer delays of the signal paths from the three supply domains. Thin-gate MOS transistors
rather than thick-gate transistors are used to support high-speed operation. In addition, three-
level supply voltages are used, and triple-well nMOS transistors are used to relax the stress on
the devices.

Fig. 3. Operating conditions of the proposed driver at steady state
The steady-state nodal voltages for the nMOS network of the output stage are described in Fig. 3.
By switching the mid and low signals simultaneously, M1 and M2 experience a gate stress of
only VDD at steady state.
SILICON PHOTONIC RECEIVER WITH A LOW SUPPLY
In a fine-line CMOS technology, the design of the amplifier is difficult owing to the following
factors. First, the reduced intrinsic gain due to the short-channel length limits the gain of the
amplifier. Second, the reduced voltage headroom makes it difficult to stack transistors and retain
a sufficient VDS. This aspect decreases ro, which is comparable with RL in the high-bandwidth
amplifier; therefore, it limits the gain of the amplifier. Moreover, the input-referred noise is

increased owing to the reduced voltage headroom, because the transconductance gm increases as
the gate-overdrive voltage decreases. Fig. 4 shows the circuit diagram of a typical common-
source (CS) amplifier and a stacked CS amplifier.
Fig. 4. Circuit diagrams of the simulated typical CS amplifier and stacked CS amplifier
Fig. 5 shows a block diagram of the proposed silicon photonic receiver. The input optical signal
illuminates a commercial PD, and the inverter-based TIA converts the PD current into a voltage-
mode signal. To minimize the supply noise sensitivity, a single-to-differential (S2D) converter is
placed at the output of the TIA. A fully differential limiting amplifier incorporating offset
cancellation feedback amplifies the signal to a full-logic level. Finally, a current-mode driver is
used to drive 50-ohms transmission lines.

Fig. 5. Block diagram of the silicon photonic receiver
Advantages:
 high energy efficiency
Software implementation:
 Tanner tools

Design of silicon photonic interconnect i cs in 65 nm cmos technology

Recomendados

Recomendados

Mais conteúdo relacionado

Destaque

Destaque (13)

Mais de Nexgen Technology

Mais de Nexgen Technology (20)

Último

Último (20)

Design of silicon photonic interconnect i cs in 65 nm cmos technology