A presentation given by Peter Levin, Consulting Professor at Stanford University.

1. Cybersecurity Peter L. Levin Consulting Professor January 2009

4. “It is a battle we are loosing”

6. Public Awareness Has Changed

7. “ several Georgian state computers [were] under external control” So they moved websites to Google:

8. P2P uses as much as 60% of Internet Bandwidth P2P networks offer an easy way to disguise illegitimate payloads using sophisticated protocols, and can divert network traffic to arbitrary ports From Spector 360

9. Machine Readable Travel Documents

10. Cracked in ten seconds for $10,000

12. The (Cyber)Security Marketplace

13. Hardware Sabotage “The most monumental non-nuclear explosion ever seen from space” was reportedly caused by the US in a Soviet commercial gas pipeline. An Israeli bombing raid on a suspected Syrian nuclear facility was (allegedly!) due to a “kill switch” that turned off surveillance radar.

14. Hardware’s Axis of Evil

16. Chip-Making in Four Easy Steps RTL & Layout Design Mask Creation Logic Circuit Design Function Specification Thanks to Grace and Sherman for this slide

17. Chip-Level Hardware Assurance Graphic from Sally Adee, IEEE Spectrum authenticity and provenance mechanical compromise add extra wires add extra transistors

18. “ Your Hands Can’t Hit What Your Eyes Can’t See” DAFCA provides on-chip, at-speed, in-system visibility

23. An Instrumented GPS Chip Trace RAM (1k x 128) Transaction Engine PTE TRACER LCD_MUX CB1_MUX aligner 4-fifo grp_lcd_out grp_lcd_fifo_rd2 grp_lcd_fifo_rd1 grp_lcd_fifo_rd3 grp_lcd_rgb grp_arm_i grp_arm_r_0 grp_usb_slv grp_usb_mstr 125 125 125 FINAL_SPN 125 CB2_MUX 125 CB3_MUX 125 125 GP_IN 2 valid bit valid bit Observation Bus = 125 (probe grp) + 2 Valid + 1 Time Stamp = 128 bit 1 valid for domain crossing of 10Mhz to 166MHz 1 valid for domain crossing of 83KHz to 166MHz SPN NETWORK 166MHz 10MHz 1 valid bit 1 valid bit 125 CDC_LCD 166MHz 166MHz CAPSTIM aligner Trace RAM (1k x 128)

24. The Road Ahead abstraction Detected Violation Software objects, pointers, calls, register writes Bus cycles, arbitration policies, event sequencing On-Chip cycle protocols and timing T T T T T T T T T T T T T T T T T T T Bus Protocol Assertions Static Mode Selects Exception Generators Memory Checkers Performance Monitors Traffic Generators Event Sequencing Boot-up System Software Application Software O c D observe characterize detect observe characterize detect