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General-purpose microprocessors are augmented with short-vector instruction extensions in order to simultaneously process more than one data element using the same operation. This type of parallelism is known as data-parallel processing. Many scientific, engineering, and signal processing applications can be formulated as matrix operations. Therefore, accelerating these kernel operations on microprocessors, which are the building blocks or large high-performance computing systems, will definitely boost the performance of the aforementioned applications. In this paper, we consider the acceleration of the matrix transpose operation using the 256-bit Intel advanced vector extension (AVX) instructions. We present a novel vector-based matrix transpose algorithm and its optimized implementation using AVX instructions. The experimental results on Intel Core i7 processor demonstrates a 2.83 speedup over the standard sequential implementation, and a maximum of 1.53 speedup over the GCC library implementation. When the transpose is combined with matrix addition to compute the matrix update, B + AT, where A and B are squared matrices, the speedup of our implementation over the sequential algorithm increased to 3.19.
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PowerPoint for subject: Microprocessor and Application, Week 1st, Introduction
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Two innovative high-speed low power parallel 8-bit counter architectures are proposed. Then, High speed 8-bit frequency divider circuits using the proposed architectures are realized. The proposed parallel counter architectures consist of two sections – The Counting Path and the State Excitation Module. The counting path consists of three counting modules in which the first module (basic module) generates future states for the two remaining counting modules. The State Excitation Module decodes the count states of the basic module and carries this decoding over clock cycles through pipelined DFF to trigger the subsequent counting modules. The existing 8-bit parallel counter architecture [1] consumed a total transistor count of 442 whereas the proposed parallel counters consumed only 274 transistors. The power dissipation of the existing parallel counter architecture and the proposed parallel counter architecture were 4.21mW (PINT) and 3.60mW (PINT) respectively at 250MHz. The worst case delay observed for the 8-bit counter using existing parallel counter architecture [1] and the proposed parallel counter architectures were 7.481ns, 6.737ns and 6.677ns respectively using Altera Quartus II. A reduction in area (transistor count) by 27.45% and a reduction in power dissipation by 16.28% are achieved for the frequency dividers using proposed counter architectures. Also a reduction in delay by 10.75% and 7.62% is achieved for the 8-bit frequency divider circuits using proposed counter methods I & II respectively.
High Speed 8-bit Counters using State Excitation Logic and their Application ...
High Speed 8-bit Counters using State Excitation Logic and their Application ...
International Journal of Science and Research (IJSR)
Now a days images are prodigiously and sizably voluminous in size. So, this size is not facilely fits in applications. For that image compression is require. Image Compression algorithms are more resource conserving. It takes more time to consummate the task of compression. Utilizing Parallel implementation of the compression algorithm this quandary can be overcome. CUDA (Compute Unified Device Architecture) Provides parallel execution for algorithm utilizing the multi-threading. CUDA is NVIDIA`s parallel computing platform. CUDA uses GPU (Graphical Processing Unit) for the parallel execution. GPU have the number of the cores for parallel execution support. Image compression can additionally implemented in parallel utilizing CUDA. There are number of algorithms for image compression. Among them DWT (Discrete Wavelet Transform) is best suited for parallel implementation due to its more mathematical calculation and good compression result compare to other methods. In this paper included different parallel techniques for image compression. With the actualizing this image compression algorithm over the GPU utilizing CUDA it will perform the operations in parallel. In this way, vast diminish in processing time is conceivable. Furthermore it is conceivable to enhance the execution of image compression algorithms.
A Review on Image Compression in Parallel using CUDA
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PowerPoint for subject: Microprocessor and Application, Week 1st, Introduction
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Arkhom Jodtang
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Two innovative high-speed low power parallel 8-bit counter architectures are proposed. Then, High speed 8-bit frequency divider circuits using the proposed architectures are realized. The proposed parallel counter architectures consist of two sections – The Counting Path and the State Excitation Module. The counting path consists of three counting modules in which the first module (basic module) generates future states for the two remaining counting modules. The State Excitation Module decodes the count states of the basic module and carries this decoding over clock cycles through pipelined DFF to trigger the subsequent counting modules. The existing 8-bit parallel counter architecture [1] consumed a total transistor count of 442 whereas the proposed parallel counters consumed only 274 transistors. The power dissipation of the existing parallel counter architecture and the proposed parallel counter architecture were 4.21mW (PINT) and 3.60mW (PINT) respectively at 250MHz. The worst case delay observed for the 8-bit counter using existing parallel counter architecture [1] and the proposed parallel counter architectures were 7.481ns, 6.737ns and 6.677ns respectively using Altera Quartus II. A reduction in area (transistor count) by 27.45% and a reduction in power dissipation by 16.28% are achieved for the frequency dividers using proposed counter architectures. Also a reduction in delay by 10.75% and 7.62% is achieved for the 8-bit frequency divider circuits using proposed counter methods I & II respectively.
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International Journal of Science and Research (IJSR)
Now a days images are prodigiously and sizably voluminous in size. So, this size is not facilely fits in applications. For that image compression is require. Image Compression algorithms are more resource conserving. It takes more time to consummate the task of compression. Utilizing Parallel implementation of the compression algorithm this quandary can be overcome. CUDA (Compute Unified Device Architecture) Provides parallel execution for algorithm utilizing the multi-threading. CUDA is NVIDIA`s parallel computing platform. CUDA uses GPU (Graphical Processing Unit) for the parallel execution. GPU have the number of the cores for parallel execution support. Image compression can additionally implemented in parallel utilizing CUDA. There are number of algorithms for image compression. Among them DWT (Discrete Wavelet Transform) is best suited for parallel implementation due to its more mathematical calculation and good compression result compare to other methods. In this paper included different parallel techniques for image compression. With the actualizing this image compression algorithm over the GPU utilizing CUDA it will perform the operations in parallel. In this way, vast diminish in processing time is conceivable. Furthermore it is conceivable to enhance the execution of image compression algorithms.
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机上の Kubernetes - 形式手法で見るコンテナオーケストレーション #NGK2016B
机上の Kubernetes - 形式手法で見るコンテナオーケストレーション #NGK2016B
形式手法で捗る!インフラ構成の設計と検証
形式手法で捗る!インフラ構成の設計と検証
FLY ASH CONCRETE
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Carbon nanotubes (1)
Carbon nanotubes (1)
Goetech. engg. Ch# 03 settlement analysis signed
Goetech. engg. Ch# 03 settlement analysis signed
Flexural design of beam...PRC-I
Flexural design of beam...PRC-I
Flexural design of Beam...PRC-I
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notes
COA Complete Notes.pdf
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kamleshAgrahari3
An arithmetic logic unit acts as the basic building blocks or cell of a central processing unit of a computer. And it is a digital circuit comprised of the basic electronics components, which is used to perform various function of arithmetic and logic and integral operations further the purpose of this work is to propose the design of an 8-bit ALU which supports 4-bit multiplication. Thus, the functionalities of the ALU in this study consist of following main functions like addition also subtraction, increment, decrement, AND, OR, NOT, XOR, NOR also two complement generation Multiplication. And the functions with the adder in the airthemetic logic unit are implemented using a Carry Look Ahead adder joined by a ripple carry approach. The design of the following multiplier is achieved using the Booths Algorithm therefore the proposed ALU can be designed by using verilog or VHDL and can also be designed on Cadence Virtuoso platform.
Implementation of an arithmetic logic using area efficient carry lookahead adder
Implementation of an arithmetic logic using area efficient carry lookahead adder
VLSICS Design
COA
COA.pptx
COA.pptx
SumitKumarYadav87201
Redes
MininetasSDNPlatform.pdf
MininetasSDNPlatform.pdf
Fernando Velez Varela
Pbl project
Gourp 12 Report.pptx
Gourp 12 Report.pptx
ShubhamMane733576
The development and miniaturization of CMOS (microphones and cameras) in the last years have allowed the creation of WMSN (Wireless Multimedia Sensor Network). Therefore, transferring multimedia content through the network has become an important field of research. It transmits the recorded multimedia data wirelessly from a node to another to reach the Sink (base station). Thus, routing protocols make a big contribution in this process, because they participate in optimizing the node's resource usage. Since Leach protocol was designed only to minimize energy consumption of the network. The goal of this paper is to compare our protocol in tnansfering images with other Leach protocol descendants. By using the application layer, we applied the jpeg compression using the frequency domain on images before sending them to the network. In this paper, readers will find statistics concerning the lifetime of the network, the energy consumption and most importantly statistics about received images. Also, we used Castalia framework to simulate real conditions of transmission simulation results proved the efficiency of our protocol by prolonging the lifetime of the network and transmitting more images with better quality compared to other protocols.
Comparing ICH-leach and Leach Descendents on Image Transfer using DCT
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IJECEIAES
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Investigating the Performance of NoC Using Hierarchical Routing Approach
Investigating the Performance of NoC Using Hierarchical Routing Approach
IJERA Editor
The Network-on-Chip (NoC) model has appeared as a revolutionary methodology for incorporatingmany number of intellectual property (IP) blocks in a die. As said by the International Roadmap for Semiconductors (ITRS), it is must to scale down the device size. In order to reduce the device long interconnection should be avoided. For that, new interconnect patterns are need. Three-dimensional ICs are proficient of achieving superior performance, resistance against noise and lower interconnect power consumption compared to traditional planar ICs. In this paper, network data routed by Hierarchical methodology. We are analyzing total number of logic gates and registers, power consumption and delay when different bits of data transmitted using Quartus II software.
Investigating the Performance of NoC Using Hierarchical Routing Approach
Investigating the Performance of NoC Using Hierarchical Routing Approach
IJERA Editor
Generation of Computer Network
Generation of Computer Network
Generation of Computer Network
Bathshebaparimala
Here we learn programmed real time load switching using rtc
Programmable Load Shedding for the utility department
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Mukund Hundekar
Optical computing
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Sandhya Shree
DESCRIPTION ABOUT CNTFET TECHNOLOGY
5. CNTFET-based design of ternary.pdf
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Raghu Vamsi
High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts.
HIGH SPEED MULTIPLE VALUED LOGIC FULL ADDER USING CARBON NANO TUBE FIELD EFFE...
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YOU CAN TAKE ADVANTAGE
COMPUTER ORGNIZATION AND ASSEMBLY LANGUAGE EBOOK
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gangesh sharma
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empirical analysis modeling of power dissipation control in internet data ce...
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saadjamil31
In this paper, the design and analysis of dual-mode numerically controlled oscillators (NCO) based controlled oscillator frequency Modulation is implemented. Initially, input is given to the analog to digital converter (ADC) converter. This will change the input from analog to digital converter. After that, the pulse skipping mode (PSM) logic and proportional integral (PI) are applied to the converted data. After applying PSM logic, data is directly transferred to the connection block. The proportional and integral block will transfer the data will be decoded using the decoder. After decoding the values, it is saved using a modulo accumulator. After that, it is converted from one hot residue (OHR) to binary converter. The converted data is saved in the register. Now both data will pass through the gate driver circuit and output will be obtained finally. From simulation results, it can observe that the usage of metal oxide semiconductor field effect transistors (MOSFETs) and total nodes are very less in dual-mode NCO-based controlled oscillator frequency modulation.
Design and analysis of dual-mode numerically controlled oscillators based co...
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IJECEIAES
Resumen de los principales temas de arquitectura de computadoras
arquitectura de computadoras
arquitectura de computadoras
Benjamín Joaquín Martínez
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip
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The Project entitled “PHARMACY MANAGEMENT SYSTEM” is systematic approach made towards maintaining purchase details, stock details, order details, sales details, sales return details, payment details, buyer details, the record are manually maintained id’s provide lots of problem. Hence we need of data to be computerized.
Pharmacy management system project report..pdf
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Kamal Acharya
Software Engineering - Part 2 which describes the following topics: Introduction, Modelling Concepts and Class Modelling: What is Object orientation? What is OO development? OO Themes; Evidence for usefulness of OO development; OO Modelling history. Modelling as Design technique: Modelling, abstraction, The Three models. Class Modelling: Object and Class Concept, Link and associations concepts, Generalization and Inheritance, A sample class model, Navigation of class models, and UML diagrams. Building the Analysis Models: Requirement Analysis, Analysis Model Approaches, Data Modelling Concepts.
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Dr. Gurudutt Sahni is a distinguished professional with an impressive array of qualifications and achievements. He holds a Ph.D. in Mechanical Engineering and a Post-Doctorate from the prestigious Indian Institute of Technology (IIT). Additionally, he has earned an MBA and a Doctorate in Management Studies, demonstrating his interdisciplinary expertise (DR PROF ING GURUDUTT SAHNI Phd,PDF) (DR PROF ING GURUDUTT SAHNI Phd,PDF). Dr. Sahni is recognized as a Chartered Engineer by the Institution of Engineers (India) and a Professional Engineer by the Engineering Council of India. His commitment to quality and safety is reflected in his numerous Lead Auditor certifications in Quality Management Systems, Energy Management Systems, and Occupational Health and Safety Management Systems (DR PROF ING GURUDUTT SAHNI Phd,PDF). His professional accolades include being named an "Outstanding Scientist" by the Science Father organization at the NESIN 2021 International Awards. He has also been honored with the Bharat Gaurav Award for his exceptional contributions to engineering and research. Dr. Sahni has made significant contributions to his field, earning the titles of Incredible Scientist of India and Incredible Researcher of India, and has been recognized by the Phoenix International World Record (CTN PRESS) (DR PROF ING GURUDUTT SAHNI Phd,PDF). Dr. Sahni's professional development includes participation in various national and international webinars and short-term courses on topics such as project risk management, cyber security, smart manufacturing, and advanced materials (DR PROF ING GURUDUTT SAHNI Phd,PDF). Dr. Gurudutt Sahni has received numerous awards and accolades throughout his distinguished career in engineering and research. Some of his notable awards include: Outstanding Scientist Award: This prestigious award was presented to him by Science Father at the NESIN 2021 International Awards (CTN PRESS). Bharat Gaurav Award: This award recognizes his significant contributions and excellence in his field (DR PROF ING GURUDUTT SAHNI Phd,PDF). EET CRS Award for Asia's Top 50 Scientists and Top 50 Researchers: These awards highlight his standing among the leading scientists and researchers in Asia (DR PROF ING GURUDUTT SAHNI Phd,PDF). Best Research Excellence Award and Best Mentor Award: These were conferred by the Research Education Society (RES) for his outstanding research and mentorship (DR PROF ING GURUDUTT SAHNI Phd,PDF). MBR Honorary Doctorate Award: Awarded by the Magic Book of Record in recognition of his contributions to his field (Magic Book of Record). These awards reflect his broad impact on both the academic and practical aspects of mechanical engineering and management studies.
DR PROF ING GURUDUTT SAHNI WIKIPEDIA.pdf
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DrGurudutt
This project aims at the Introduction to app Service Management. This software is designed keeping in mind the user’s efficiency & ease of handling and maintenance , as and secured system over centralized data handling and providing with the features to get the complete study and control over the business. The report depicts the basics logic used for software development long with the Activity diagrams so that logics may be apprehended without difficulty. For detailed information, screen layouts, provided along with this report can be viewed. Although this report is prepared with considering the results required these may be across since the project is subjected to future enhancements as per the need of organizations.
Online resume builder management system project report.pdf
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Kamal Acharya
Talk in the DevOpsPro Europe 2024 at Vilnius
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Paco Orozco
this is the internship report on embedded system and IOT
internship exam ppt.pptx on embedded system and IOT
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NavyashreeS6
Online movie ticket booking system for movies is a web-based program. This application allows users to purchase cinema tickets over the portal. To buy tickets, people must first register or log in. This website's backend is PHP and JavaScript, and the front end is HTML and CSS. All phases of the software development life cycle are efficiently managed in order to design and implement software. On the website, there are two panels: one for administrators and one for customers/users. The admin has the ability to add cinemas, movies, delete, halt execution, and add screens, among other things. The website is simple to navigate and appealing, saving the end user time.
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Building accurate #LLM driven application is tough, current solution suffer from low accurary issues due to inherited design flaws,. Switching from the current solution which used #VectorDB to #KnowledgeGraph will boots your answers accuracy, see why.
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Roi Lipman
Our vision is to make ONLINE CAR SERVICING SYSTEM is needed for the country as technology grows fast in the world. The purpose is to develop this project to provide a better solution to the problems that the customers faces. This website will provide customers to reserve their car services from their home or from office. Customer feels hard to send their car for the service, either they need to reserve using mail system or walk in to send their car for service. At the end of these project, a prototype of justified system will develop which will provide a solution for the identify problem to improve the organizations revenue and performance. This system will be web based system where it is able to conduct an overall process of online registration and bookings too. The data will be stored in keep as privacy for each customer who has register.
ONLINE CAR SERVICING SYSTEM PROJECT REPORT.pdf
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Kamal Acharya
read it
Digital Signal Processing Lecture notes n.pdf
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AbrahamGadissa
İTÜ CAD and Reverse Engineering Workshop
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Emre Günaydın
UofT毕业证【微信95270640】☀《多伦多大学毕业证购买》GoogleQ微信95270640《UofT毕业证模板办理》加拿大文凭、本科、硕士、研究生学历都可以做,二、业务范围: ★、全套服务:毕业证、成绩单、化学专业毕业证书伪造《多伦多大学大学毕业证》Q微信95270640《UofT学位证书购买》 [留学文凭学历认证(留信认证使馆认证)多伦多大学毕业证成绩单毕业证证书大学Offer请假条成绩单语言证书国际回国人员证明高仿教育部认证申请学校等一切高仿或者真实可查认证服务。 多年留学服务公司,拥有海外样板无数能完美1:1还原海外各国大学degreeDiplomaTranscripts等毕业材料。海外大学毕业材料都有哪些工艺呢?工艺难度主要由:烫金.钢印.底纹.水印.防伪光标.热敏防伪等等组成。而且我们每天都在更新海外文凭的样板以求所有同学都能享受到完美的品质服务。 国外毕业证学位证成绩单办理方法: 1客户提供办理多伦多大学多伦多大学本科学位证成绩单信息:姓名生日专业学位毕业时间等(如信息不确定可以咨询顾问:我们有专业老师帮你查询); 2开始安排制作毕业证成绩单电子图; 3毕业证成绩单电子版做好以后发送给您确认; 4毕业证成绩单电子版您确认信息无误之后安排制作成品; 5成品做好拍照或者视频给您确认; 6快递给客户(国内顺丰国外DHLUPS等快读邮寄) — — — — 我们是挂科和未毕业同学们的福音我们是实体公司精益求精的工艺! — — — - 一真实留信认证的作用(私企外企荣誉的见证): 1:该专业认证可证明留学生真实留学身份同时对留学生所学专业等级给予评定。 2:国家专业人才认证中心颁发入库证书这个入网证书并且可以归档到地方。 3:凡是获得留信网入网的信息将会逐步更新到个人身份内将在公安部网内查询个人身份证信息后同步读取人才网入库信息。 4:个人职称评审加20分个人信誉贷款加10分。 5:在国家人才网主办的全国网络招聘大会中纳入资料供国家500强等高端企业选择人才。的小鸟叽叽咋咋的叫声是否就是这最后的点睛之笔悠然走在林间的小路上宁静与清香一丝丝的盛夏气息吸入身体昔日生活里的繁忙与焦躁早已淡然无存心中满是悠然清淡的芳菲身体不由的轻松脚步也感到无比的轻快走出这盘栾交错的小道眼前是连绵不绝的山峦浩荡天地间大自然毫无吝啬的展现它的磅礴与绚美淡淡熏香细腻游滑的飘荡在鼻尖茂密的树木遍布起立在漫山遍野绿幽幽的景色这是盛夏才有的芳菲啊宁静之中悠然的心情多了些许阔达想起那些阳
一比一原版(UofT毕业证)多伦多大学毕业证成绩单
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tuuww
NO1 Pandit Black Magic Removal in Uk kala jadu Specialist kala jadu for Love Back kala ilm Specialist Black Magic Baba Near Me +92322-6382012
NO1 Pandit Black Magic Removal in Uk kala jadu Specialist kala jadu for Love ...
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Amil baba
Its an "United Nations Park" Construction site. We have visited this place to gain some practical experience which is related to our academic topic. In this site we have seen a various engineering materials like hollow bricks, Concrete block, plain tiles. And how to make a water fountain, and pathway which is aesthetically pleasing to see. This construction was directed by our Honorable Sir Md. Abul Hasan. The Name of the developer is "STRUCXEL" which have the glorious history in the development in Chittagong.
"United Nations Park" Site Visit Report.
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Design of columns
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HamzaKhawar4
List of Best Scientist Who Gives Big Contribution in Civil Engineering Filed, in this we provide how they Contribute in Civil Engineering filed, For Data Collection civilthings.com helps us a lot.
Top 13 Famous Civil Engineering Scientist
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gettygaming1
This PPT is prepared for VTU-Karnataka, Mtech/PhD Research Methodology syllabus based on C.R. Kothari, Gaurav Garg, Research Methodology: Methods and Techniques, New Age International, 4th Edition, 2018
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T.D. Shashikala
Electronic Shop Management software helps Electronic showrooms owners and management staff by producing different kind of financial and stock tracking reports, etc. This software is able to manage all electronic stocks. In this software shop owner can manage the data of customer and buyers. Also tax information and other government charges including recycle charges. Electrical shop management system is workable application for retail store inventory and account management. It keeps a list STOCKS and products at a store and can do operation on them. The most important operation on them. The most important operation is a PURCHASE, all the transactions and the billing details and stock purchasing details involved on it
Electrical shop management system project report.pdf
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Kamal Acharya
Frame Works and Visualization
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Pharmacy management system project report..pdf
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Carbon nanotube
1.
LETTER doi:10.1038/nature12502 Carbon nanotube
computer Max M. Shulaker1 , Gage Hills2 , Nishant Patil3 , Hai Wei4 , Hong-Yu Chen5 , H.-S. Philip Wong6 & Subhasish Mitra7 The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency.Althoughadvances withsilicon-basedelectronics continue to be made, alternative technologies are being explored. Digital cir- cuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy– delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies1,2 . Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfec- tions can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstra- tion, we perform counting and integer-sorting simultaneously. In addition, we implement 20different instructions from the commer- cial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems3,4 . CNTs are hollow, cylindrical nanostructures composed of a single sheet of carbon atoms, and have exceptional electrical, physical and thermal properties5–7 . They can be used to fabricate CNT field-effect transistors (CNFETs), which are promising candidate building blocks forthenextgenerationofhighlyenergy-efficientelectronics1,2,8 :CNFET- baseddigitalsystemsarepredictedtobeabletooutperformsilicon-based complementary metal–oxide–semiconductor (CMOS) technologies by more than an order of magnitude in terms of energy–delay product, a measure of energy efficiency2–4 . Since the initial discovery of CNTs, there have been several major milestones for CNT technologies9 : CNFETs, basic circuit elements (logic gates), a five-stage ring oscillator fabricated along a single CNT, apercolation-transport-baseddecoder,stand-alonecircuitelementssuch as half-adder sum generators and D-latches, and a capacitive sensor interface circuit10–16 . Yet there remains a serious gap between these circuit demonstrations for this emerging technology and the first com- puters built using silicon transistors, such as the Intel 4004 and the VAX-11 (1970s). These silicon-based computers were fundamentally different from the above-mentioned CNFET-based circuits in several key ways: they ran stored programs, they were programmable (mean- ing that they could execute a variety of computational tasks through proper sequencing of instructions without modifying the underlying hardware17 )andtheyimplementedsynchronousdigitalsystemsincorpo- rating combinational logic circuits interfaced with sequential elements such as latches and flip-flops18 . It is well known that substantial imperfections inherent in CNT technology are the main obstacles to the demonstration of robust and complex CNFET circuits19 . These include mis-positioned and metallic CNTs. Mis-positioned CNTs create stray conducting paths leading to incorrect logic functionality, whereas metallic CNTs have little or no bandgap, resulting in high leakage currents and incorrect logic functionality20 .Theimperfection-immunedesignmethodology,which combines circuit design techniques with CNT processing solutions, overcomes these problems20,21 . It enables us to demonstrate, for the first time, a complete CNT computer, realized entirely using CNFETs. Similartothefirstsilicon-basedcomputers,ourCNTcomputer,whichis a synchronous digital system built entirely from CNFETs, runs stored programs and is programmable. Our CNT computer runs a basicopera- ting system that performs multitasking, meaning that it can execute multipleprogramsconcurrently (inan interleaved fashion). We demon- strateourCNTcomputerbyconcurrentlyexecutingacountingprogram and an integer-sorting program (coordinated by a basic multitasking operating system), and also by executing 20 different instructions from the commercial MIPS instruction set22 . The CNT computer is a one-instruction-set computer, implement- ing the SUBNEG (subtract and branch if negative) instruction, inspired byearlyworkinref.23.WeimplementtheSUBNEGinstructionbecause it is Turing complete and thus can be used to re-encode and perform any arbitrary instruction from any instruction-set architecture, albeit at the expense of execution time and memory space24,25 . The SUBNEG instruction is composed of three operands: two data addresses and a third partial next instruction address (the CNT computer itself com- pletes the next instruction address, allowing for branching to different instruction addresses). The SUBNEG instruction subtracts the value of the data stored in the first data address from the value of the data stored in the second data address, and writes the result at the location of the second data address. The next instruction address is calculated to be one of two possible branch locations, depending on whether the result of the subtraction is negative. The partial next instruction address given by the present SUBNEG instruction omits the least significant bit. The least signifi- cant bit is calculated by the CNT computer, on the basis of whether the result of the SUBNEG subtraction was negative. This bit, concatenated with the partial next instruction address given in the SUBNEG instruc- tion, makes up the entire next instruction address. A diagram showing the SUBNEG implementation is shown in Fig. 1a. As our operating system, weimplementnon-pre-emptivemultitask- ing, whereby each program performs a self-interrupt and voluntarily gives control to another task26 . To perform this context switch, the instruction memory is structured in blocks, and each block contains a different program. To perform the self-interrupt, the running program stores a next instruction address belonging to a different program block; thus, the other program begins execution at this time. During the context switch, the CNT computer updates a process ID bit in memory, which indicates the program running at present. An example of the operating system running two different programs concurrently is shown in Fig. 1b. ThecircuitryoftheCNTcomputerisentirelycomposedofCNFETs, and the instruction and data memories are implemented off-chip, following the von Neumann architecture and the convention of most computers today. The off-chip memories perform no operation other 1 Stanford University, Gates Building, Room 331, 353 Serra Mall, Stanford, California 94305, USA. 2 Stanford University, Gates Building, Room 358, 353 Serra Mall, Stanford, California 94305, USA. 3 SK Hynix Memory Solutions, 3103 North First Street, San Jose, California 95134, USA. 4 Stanford University, Gates Building, Room 239, 353 Serra Mall, Stanford, California 94305, USA. 5 Stanford University, Paul G. Allen Building, Room B113X, 420 Via Ortega, Stanford, California 94305, USA. 6 Stanford University, Paul G. Allen Building, Room 312X, 420 Via Ortega, Stanford, California 94305, USA. 7 Stanford University, Gates Building, Room 334, 353 Serra Mall, Stanford, California 94305, USA. 5 2 6 | N A T U R E | V O L 5 0 1 | 2 6 S E P T E M B E R 2 0 1 3 Macmillan Publishers Limited. All rights reserved©2013
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than performing a
single read or a single write in a clock cycle. The address, data(forwrite),andread andwrite enablesignals are provided by the CNT computer; the values, once read, are stored in D-latches in the CNT computer, built entirely using CNFETs. A full schematic of the CNT computer is shown in Fig. 2a. The CNT computer performs four tasks. (1) Instruction fetch: this task supplies instruction memory with the address to read. On the first clock (Clock1), the SUBNEG instruction is readfromtheinstructionmemoryandsavedinabankoftenD-latches. The SUBNEG instruction contains the partial next instruction address (as explained above), and the addresses of the two single-bit data values to operateon(representedas[A]and[B],bothofwhichcomprisethreebits). (2) Data fetch: this task supplies the data memory with the addresses given by the SUBNEG instruction to read. On Clock1, the first data address ([A]) is read and the value is saved in a D-latch. On the second clock (Clock2), the second data address ([B]) is read and the value is saved in another D-latch. (3) Arithmetic operation: this task performs the computation (sub- traction and comparison with zero) on the two data values supplied by the data-fetch unit. Program 0: counter Program 0: counter Context switch Next instruction address [MSB] = 0 → 1 Context switch Next instruction address [MSB] = 0 → 1 Program 1: Bubble-sort (x0, x1) Program 1: Bubble-sort (x1, x2) Data address (A) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 01 1 1 0 0 0 0 0 0 01 1 1 0 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 01 1 1 0 1 1 1 1 10 0 0 0 0 1 0 0 0 0 0 01 1 1 1 0 0 0 0 0 01 0 0 0 0 0 01 1 1 1 0 0 0 1 1 1 10 0 0 0 0 1 1 1 1 1 10 0 0 0 1 1 1 1 1 10 0 0 0 1 1 1 1 1 00 0 0 1 1 0 1 1 1 10 0 0 0 0 0 0 0 1 1 10 0 0 0 0 0 1 1 1 1 1 1 1 10 0 1 1 1 1 1 1 1 10 0 1 1 1 1 1 1 1 00 1 1 0 0 0 0 01 1 1 1 1 0 0 0 0 0 0 0 00 1 1 0 0 0 0 0 0 00 1 1 0 0 0 01 1 1 1 1 1 1 1 0 1 1 01 1 0 1 1 10 0 0 0 0 1 1 1 10 0 0 0 0 0 1 0 1 01 1 0 1 0 1 1 1 10 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0 01 1 1 0 0 0 0 0 11 0 1 0 0 0 0 0 0 0 0 0 0 Data address (B) Next instruction address MSB LSB MSB dictates present process Instruction fetch SUBNEG (Address(A), Address(B), next instruction address [4:1]) Data fetch (values of A and B) Context switch Next instruction address [MSB] = 1 → 0 Context switch Next instruction address [MSB] = 1 → 0 a b Arithmetic operation (B – A) B – A < 0 B – A ≥ 0 Next instruction address [0] = 1 Write-back (B – A) at address(B) Next instruction address [0] = 0 Write-back (B – A) at address(B) Next instruction address [4:0] Nextinstructionaddress[0]calculatedfrom arithmeticunit 1 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 Figure 1 | SUBNEG and program implementation. a, Flowchart showing the implementation of the SUBNEG instruction. b, Sample program on CNT computer. Each row of the chart is a full SUBNEG instruction. It is composed of two data addresses and a partial next instruction address. The (omitted) least significant bit (LSB) of the next instruction address is calculated by the arithmetic unit of the CNT computer, and the most significant bit (MSB) of the next instruction address indicates the running program, either a counter or bubble-sort algorithm in this instance. Instruction fetch Data fetch Arithmetic operation Write- back Data address [B] [2:0] Next instruction address [4:1] Data address [A] [2:0] Next instruction address [0] CLK2 CLK3 A B Write-back CLK1 a b Instruction memory RD_en WR_en Out CLK1 CLK1 10 3 3 4 Next instruction address [4:1] [0] RD_A_en [A] Data memory CLK1 3 3 B A 1 1 A CLK1 CLK2 B A A·B A ⊕ B 1 1 CLK3 CLK3 CLK3 D-latches D-latches D-latches CLK2 CLK3 RD_B_en WR_en [B] Data_in B[B] [2:0] [A] [2:0] Nextinstruction address [4:1] Nextinstruction address [4:1] D D D D Q Q Q Q G G D Q D Q G G D Q D Q G G Figure 2 | Schematic of CNT computer. a, Schematic of the entire CNT computer, composed of the four subunits: instruction fetch, data fetch, arithmetic operation and write-back. All components apart from the memory are implemented entirely using CNFETs. CLK1–CLK3, Clock1–Clock3; D, D-latch input; Q, D-latch output; G, D-latch clock; RD_en, read enable (instruction memory); WR_en, write enable (instruction memory); RD_A_en, read enable address A (data memory); RD_B_en, read enable address B (data memory); Data_in, data for data memory write. b, Timing diagram of the CNT computer. The lines show the waveforms corresponding to each signal; of particular note are the transitions of the lower five signals with respect to the clock signals. LETTER RESEARCH 2 6 S E P T E M B E R 2 0 1 3 | V O L 5 0 1 | N A T U R E | 5 2 7 Macmillan Publishers Limited. All rights reserved©2013
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(4) Write-back: this
task writes back the result of the SUBNEG (B 2 A) in the data memory at the address of the second data address. On the third clock (Clock3), the result from the arithmetic-operation unit is saved in two D-latches. Simultaneously, Clock3 enables the write-back to the data memory. D-latches from the instruction-fetch unit supply the data address, and the D-latch from the write-back stage supplies the value to be written. A timing diagram depicting the above description and using three non-overlapping clocks is shown in Fig. 2b. TheCNFETcomputeriscomposedof178CNFETs,witheachCNFET comprising ,10–200 CNTs, depending on relative sizing of the widths of the CNFETs. Figure 3 shows transistor-level schematics of the sub- components, D-latches and the arithmetic unit. We use logic circuits that use only p-type transistors, because our CNFETs are p-type with- out modifications. Consequently, relative sizing of the widths of pull- up and pull-down CNFETs is crucial; the ratio of all pull-up CNFET widths to pull-down CNFET widths in our design is either 20:1 or 10:1 (Methods). There is a maximum of seven stages of cascaded logic in the computer, demonstrating our ability to cascade combinational logic stages, which is a necessity in realizing large digital systems. TheCNT-specificfabricationprocessisbasedontheprocessdescribed inrefs21,23,27,and isdescribed indetailinMethods. Importantly,the fabrication process is completely silicon-CMOS compatible owing to its low thermal budget (125 uC). We use standard cells for our sub- systems, designed following the imperfection-immune methodology, which rendersour circuits immunetobothmis-positioned and metallic CNTs. Because this method ensures that the immunity to CNT imper- fections is encapsulated entirely within standard cells, the fabrication is completely insensitive to the exact positioning of CNTs on the wafer and there is no per-unit customization, rendering our processing and design VLSI (very large-scale integration) compatible. The entire CNT computer is fabricated completely within a die on a single wafer. Each die contains five CNT computers, and each wafer contains 197 dies. There is no customization of any sort after circuit fabrication: all of the CNFETsandinterconnectsarepredeterminedduringdesign,andthereis no post-fabrication selection, configuration or fine-tuning of functional CNFETs. Just like any von Neumann computer, off-chip interconnects areused forconnectionstoexternalmemories.OurCNT-specificfabri- cation process and imperfection-immune design enables high yield and robust devices; waveforms of 240 subsystems (40 arithmetic logic units and 200 D-latches) from across a wafer are shown in Fig. 3. The yield of the subsystems, such as D-latches, typicallyranges from80% to 90%. The primary causes of yield loss—particles resulting in broken lithography patterns, adhesion issues with metal lift-off and variations in machineetchrates—are consequencesof the limitationsof perform- ing all fabrication steps in-house in an academic fabrication facility. A SEM image of a fabricated CNT computer is shown in Fig. 4a. To demonstrate theworking CNT computer, we perform multitasking with our basic operating system, concurrently running a counter program andan integer-sortingprogram(performingthebubble-sortalgorithm). Although CNFET circuits promise improved speed2,4,8 , our computer runs at 1 kHz. This is not due to the limitations of the CNT technology or our design methodology, but instead is caused by capacitive loading introduced by the measurement setup, the 1-mm minimum lithogra- phic feature size possiblein our academic fabrication facility,and CNT density and contact resistance (Methods). The measured and expected VB VB VB Source Drain CNTs Drain–source voltage, VDS (V) D D D D Q Q Q Q A B AND XOR 90μm 90μm 1μm CLK CLK VDD VB GND A B AB 4D-latches CNFET Draincurrent,ID(μA) 00 400 Time (ms)Time (ms) 3 V 3 V 3 V 3 V 3 V CLK Q 3 V 3 V 12 D a b c A A B A VDD VDD A! B! B! XOR AND CLK! CLK D VB Q 8 8 8 8 8 8 8 8 80 160 160 160160 160 80 80 80 80 80 80 80 80 160 160 8 VDD = 3 V VB = –5 V Gate voltage, VGS (V) 0–3 –1.5 10 10–2 10–5 VDS = –3 V –8 V –6 V –4 V –2 V 0 V VGS = 0–5 –3 20 40 0 B A! B! 8080 A ⊕ B Figure 3 | Characterization of CNFET subcomponents. a, Top: Final 4-inch wafer after all fabrication. Middle: scanning electron microscope (SEM) image of a CNFET, showing source, drain and CNTs extending into the channel region. Bottom, Measured characterization (current–voltage) curves of a typical CNFET. The yellow highlighted region of the ID–VDS curve shows the biasing region that the CNFET operates in for the CNT computer. b, Top: transistor-level schematic of arithmetic unit. Numbers are width of transistors (in micrometres). Middle: SEM of an arithmetic unit. Bottom: measured outputs from 40 different arithmetic units, all overlaid. c, Top: transistor-level schematic of D-latches. Numbers are width of transistors (in micrometres). Middle: SEM of a bank of 4 D-latches. Bottom: measured outputs from 200 different D-latches, all overlaid. RESEARCH LETTER 5 2 8 | N A T U R E | V O L 5 0 1 | 2 6 S E P T E M B E R 2 0 1 3 Macmillan Publishers Limited. All rights reserved©2013
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outputs from the
CNT computer (Fig. 4b) show correct operation. To demonstrate the flexibility and ability of the SUBNEG computer to implement any arbitrary instruction, we additionally perform 20 MIPS instructions (Fig. 4c) on the CNT computer. Although the CNT com- puter operates on single-bit data values, this is not a fundamental limi- tation, because any multibit computation can be performed with a single-bit computer through serial computation23 . Additionally, having shown the ability to cascade logic, fabricating a larger multibit CNT computer is not a fundamental obstacle, but rather affects only yield; as a demonstration, we show a two-bit arithmetic logic unit (composed of 96CNFETswithamaximumof15stagesofcascadedlogic)inExtended Data Fig. 2 (see also Methods). We have reported a CNT computerfabricated entirely from CNFETs, and have demonstrated its ability to run programs, to run a basic opera- ting system that performs multitasking, and to execute MIPS instructions. To achieve this we used the imperfection-immune design methodo- logy and developed robust and repeatable CNT-specific design and processing. This demonstration confirms that CNFET-based circuits are a feasible and plausible emerging technology. METHODS SUMMARY The fabrication process is depicted in Extended Data Fig. 1. The CNTs are grown on a quartz substrate to yield highly aligned CNTs14 , and are transferred onto the target SiO2 wafer14 . Before CNT transfer, the wafer undergoes processing to define bottom-layer wires and the local back gates of the transistors28 . Lithographically defined trenches are etched using a combination of dry plasma etch followed by wet etch, and are filled by electron-beam evaporation of platinum and smoothed by a subsequent plasma sputter etch. A 24-nm high-k dielectric of Al2O3 is deposited by atomic-layer deposition, and contact holes are etched through this layer to the embedded metal wires and gates through another combined dry- and wet-etch process. After CNT transfer, the source and drain (bilayers of palladium and pla- tinum) are lithographically defined through a lift-off process, and mis-positioned CNTs are etched away using optical lithography followed by oxygen plasma15 . A metal layer of gold is lithographically patterned with lift-off and connects every other source and drain, and separately connects every gate, effectively forming a single CNFET composed of all of the single CNFETs in parallel. Electrical break- down is performed once on this entire structure to remove .99.99% of metallic CNTs29,30 . This gold layer is then selectively etched away, and the top metal layer connecting the circuit in the proper configuration is lithographically patterned and deposited with lift-off. Online Content Any additional Methods, ExtendedData display items and Source Data are available in the online version of the paper; references unique to these sections appear only in the online paper. Received 12 May; accepted 24 July 2013. 1. Franklin, A. D. et al. Sub-10 nm carbon nanotube transistor. Nano Lett. 12, 758–762 (2012). 2. Wei, L., Frank, D., Chang, L. & Wong, H.-S. P. in Proc. 2009 IEEE Intl Electron Devices Meeting 917–920 (IEEE, 2009). 3. Chang, L. in Short Course IEEE Intl Electron Devices Meeting (IEEE, 2012). 4. Nikonov, D. & Young, I. in Proc. 2012 IEEE Intl Electron Devices Meeting 24–25 (IEEE, 2012). 5. Javey, A., Guo, J., Wang, Q., Lundstrom, M. & Dai, H. Ballistic carbon nanotube transistors. Nature 424, 654–657 (2003). 6. Javey, A., Wang, Q., Kim, W. & Dai, H. in 2003 Intl Electron Devices Meeting Tech. Digest 31–32 (IEEE, 2003). 7. Appenzeller, J. Carbon nanotubes for high-performance electronics—progress and prospect. Proc. IEEE 96, 201–211 (2008). 8. Deng, J. et al. in Proc. 2007 IEEE Intl Solid State Circuits Conf. 70–78 (IEEE, 2007). 9. Iijima, S. Helical microtubules of graphitic carbon. Nature 354, 56–58 (1991). 10. Martel, R. A. , Schmidt, T., Shea, H. R., Hertel, T. & Avouris, P. Single-and multi-wall carbon nanotube field-effect transistors. Appl. Phys. Lett. 73, 2447 (1998). 11. Tans, S.J., Verschueren,A.R.&Dekker, C.Room-temperature transistorbasedona single carbon nanotube. Nature 393, 49–52 (1998). 12. Chen, Z. et al. An integrated logic circuit assembled on a single carbon nanotube. Science 311, 1735 (2006). 13. Cao, Q. et al. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates. Nature 454, 495–500 (2008). 14. Patil,N., Lin, A.,Myers, E.R., Wong, H.-S. P.& Mitra, S. in Proc. Symp. VLSI Tech. 205– 206 (2008). 15. Patil, N. et al. Scalable carbon nanotube computational and storage circuits immune to metallic and mis-positioned carbon nanotubes. IEEE Trans. NanoTechnol. 10, 744–750 (2011). 16. Shulaker, M. et al. in Proc. 2013 IEEE Intl Solid State Circuits Conf. 112–113 (IEEE, 2013). 17. von Neumann, J. First draft of a report on the EDVAC. Ann. Hist. Comput. 15, 27–75 (1993). 18. McCluskey, E. J. Logic Design Principles with Emphasis on Testable Semicustom Circuits (Prentice-Hall, 1986). 19. Cao, Q. et al. Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics. Nature Nanotechnol. 8, 180–186 (2013). a Instruction fetch Data fetch Arithmetic operation Write-back b MIPS instructions Expected Measured CLK1 Addr A[0] Addr A[1] Addr A[2] Addr B[0] Addr B[1] Addr B[2] CLK1 A B B – A [0] [1] [2] [3] [4] Nextinstraddr Data fetch addresses Arithmetic result and next instruction address calculation Subtract bit Branch bit Sorter: 100 → 010 →001 →001 →001 →001 →001 Counter: 01 → 10 →11 →00 →01 →10 →11 MSB dictates present program • AND • ANDI • BGEZ • BLEZ • BLTZ • BNE • J • LB • NOOP • OR • ORI • SB • SLL • SLLV • SRA • SRLV • SRL • SUBU • XOR • XORI c 3 V 0 ms 48 ms Figure 4 | CNT computer results. a, SEM of an entire CNT computer. b, Measured and expected output waveforms for a CNT computer, running the program shown in Fig. 1b. The exact match in logic value of the measured and expected output shows correct operation. As shown by the MSB (denoted [4]) of the next instruction address, the computer is switching between performing counting and sorting (bubble-sort algorithm). The running results of the counting and sorting are shown in the rows beneath the MSB of the next instruction address. c, A list of the 20 MIPS instructions tested on the CNT computer. LETTER RESEARCH 2 6 S E P T E M B E R 2 0 1 3 | V O L 5 0 1 | N A T U R E | 5 2 9 Macmillan Publishers Limited. All rights reserved©2013
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20. Zhang, J.
et al. Robust digital VLSI using carbon nanotubes. IEEE Trans. CAD 31, 453–471 (2012). 21. Patil, N. Design and Fabrication of Imperfection-Immune Carbon Nanotube Digital VLSI Circuits. PhD thesis, Stanford Univ. (2010). 22. Patterson, D. A. & Hennessy, J. L. Computer Architecture (Kaufmann, 1990). 23. Lin, A. Carbon Nanotube Synthesis, Device Fabrication, and Circuit Design for Digital Logic Applications. PhD thesis, Stanford Univ. (2010). 24. Herken, R. (ed.) The Universal Turing Machine: A Half-Century Survey (Springer, 1995). 25. Nu¨rnberg, P., Uffe, W. & Hicks, D. A grand unified theory for structural computing. Metainformatics 3002, 1–16 (2004). 26. Jeffay, K., Donald, S. F. & Martel, C. U. in Proc. Real-Time Systems Symposium 129–139 (IEEE, 1991). 27. Shulaker, M. et al. Linear increases in carbon nanotube density through multiple transfer technique. Nano Lett. 11, 1881–1886 (2011). 28. Bachtold, A., Hadley, P., Nakanishi, T. & Dekker, C. Logic circuits with carbon nanotube transistors. Science 294, 1317–1320 (2001). 29. Collins, P. G., Arnold, M. S. & Avouris, P. Engineering carbon nanotubes and nanotube circuits using electrical breakdown. Science 292, 706–709 (2001). 30. Patil, N. et al. in Proc. 2009 IEEE Intl Electron Devices Meeting 573–576 (IEEE, 2009). Acknowledgements We acknowledge the support of the NSF (CISE) (CNS-1059020, CCF-0726791, CCF-0702343, CCF-0643319), FCRP C2S2, FCRP FENA, STARNet SONIC and the Stanford Graduate Fellowship and the Hertz Foundation Fellowship (M.M.S.). We also acknowledge Z. Bao, A. Lin, H. (D.) Lin, M. Rosenblum, and J. Zhang for their advice and collaborations. Author Contributions M.M.S. led and was involved in all aspects of the project, did all of thefabricationandlayoutdesigns,andcontributedtothedesignandtesting.G.H.wrote the SUBNEG and testing programs, and contributed to the design and testing. N.P. contributed to the design, and N.P., H.W. and H.-Y.C. contributed to developing fabrication processes. H.-S.P.W. and S.M. were in charge and advised on all parts of the project. Author Information Reprints and permissions information is available at www.nature.com/reprints. The authors declare no competing financial interests. Readers are welcome to comment on the online version of the paper. Correspondence and requests for materials should be addressed to M.M.S. (maxms@stanford.edu). RESEARCH LETTER 5 3 0 | N A T U R E | V O L 5 0 1 | 2 6 S E P T E M B E R 2 0 1 3 Macmillan Publishers Limited. All rights reserved©2013
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METHODS The fabrication process
is depicted in Extended Data Fig. 1. CNT growth and transfer. The CNTs are grown by chemical-vapour deposition with methane at 865uC.The growthsubstrate is an annealed quartzsubstrate, with parallel catalyst stripes of iron lithographically patterned on the wafer. Quartz is used to achieve 99.5% alignment of the CNTs, which align along the crystalline boundary owing to a minimized Lennard–Jones potential in this orientation14 . After growth, the quartz wafer with CNTs is coated with 150nm gold, and a thermal release tape is applied on top of the gold. When this tape is peeled from the wafer, it peels off the gold with embedded CNTs from the quartz wafer. The tape is then applied onto the target wafer and heated to 125 uC, at which point the thermal release tape losesadhesion andis removed from the wafer,leaving the gold with embedded CNTs on the target wafer. The surface of the wafer undergoes oxygen andargon plasmaetching to removeanyresidue from thetape, followedby a selective wet etch to remove the gold, leaving exposed, highly aligned CNTs on the wafer14 . Local back gate. Before transfer, the target wafer is first prepared, starting with a silicon wafer with 110nm thermal oxide growth. To form the local back gate28 and bottom layer of wires, a two-layer resist stack is lithographically patterned on the surface. Following development of the pattern, the wafer goes through a quick oxygen plasma de-scum, followed by an anisotropic O2/SF6 plasma etch. After the plasma etch, a quick HF dip is used to smooth the surface and remove any side- wall deposition from the plasma etching. Next, an adhesion layer of Ti followed by Pt is evaporated, filling the trenches etched in the previous step. The bilayer of resist is dissolved away, lifting off the extra metal and leaving the metal in the trenches. An argon sputter etch follows, and, owing to the difference in etch rate between the Pt and SiO2, the surface of the wafer is smoothed until the offset between the local back gate height and the wafer is less than a nanometre. Initial transistor fabrication. We use ,24 nm Al2O3 as our high-k back-gate die- lectric. This is deposited through atomic-layer deposition on the wafer described above, covering the local back gates and bottom-level wires. Before CNT transfer, the deposited surface undergoes an oxygen plasma etch to clean the surface of any contaminants and a forming gas anneal, followed by the CNT transfer process described above. Immediately following transfer is source–drain definition of the individual transistors. A bilayer of resist is patterned and developed, and a bilayer of 20 nm Pd and 20 nm Pt is deposited for both the source and drains. This is followed by a traditional lift-off process. In addition to the source and drain, a second layer of metal wiring is patterned and deposited. This second layer of metal wiring is permanent through the rest of the process. After the metal deposition, mis-positioned andunneeded CNTs areremoved by covering the active area of the transistors with photoresist and etching away the unprotected CNTs with oxygen plasma. The layout of the active area of the transistors follows the mis-positioned CNT immune design20,21 , and guarantees that no mis-positioned CNTs can cause incorrect logic function. This renders the circuit immune to mis-positioned CNTs. Contacts to the bottom-layer wires and local back gates are lithographically defined and etched with an Ar/CL2/BCL3 plasma etch, followed by HF dip, with the embedded metal acting as a natural etch stop. Metallic CNT removal. To ensure high Ion/Ioff ratios and correct logic function- ality, it is necessary to remove .99.99% of the metallic CNTs from the circuit, while leaving the semiconducting CNTs predominantly intact. This is achieved through electrical breakdown, which biases the gate of the transistor to turn the semiconducting CNTs off, and pulses a large current through the metallic CNTs, causing joule self-heating until the metallic CNTs oxidize and are removed, thus no longer conducting current29 . Rather than performing breakdown on the indi- vidual transistors, we employ VLSI-compatible metallic CNT removal30 (VMR). VMR allows electrical breakdown to be performed on the chip scale. To do so, we lithographicallydefineandpatternagoldlayerthroughthelift-offprocessesdescribed above. The gold is patterned to short every gate, source and drain together. This effectively forms a single large CNFET, composed of all of the single CNFETs connected in parallel. The shorted structures make use of the power rails and clock distribution networks to minimize area overhead. We then perform electrical breakdown on the entire structure once, enabling quick and efficient breakdown of hundreds of transistors and thousands of CNTs simultaneously (though this is not a fundamental limitation of the size of a VMR structure). After electrical breakdown, the gold layer is removed. The third and final metal layer of Pt with an adhesion layer of Ti is deposited and lifted off, forming the final circuit layout configuration. Test set-up. As shown in Fig. 4a, the CNT computer has four rows of probe pads, each containing 39 pads. A custom probe card is used to probe all of the pads simultaneously, although many of the pads are unused (and are simply present to ensure that the probe tips from the probe card always land on metal). Through the probe card, thepads areeither connected to a supply voltage (VDD, GND, VBIAS) or to the inputs or outputs of the computer (the address outputs and input values to and from the off-chip memories). All other connections are made on-chip, as shown in Extended Data Fig. 3. A National Instrument DAQ (data acquisition hardware, #9264) is used to interface with the probe card and read and write the inputs and, respectively, outputs to the CNT computer, and Agilent oscilloscopes (#2014A) are additionally used to record the analogue traces of the outputs of the CNT computer (Fig. 4b). Biasing.Thebiasing schemeforthe circuits is shown in Fig. 3,with VDD 5 3 V and VBIAS 5 25 V. There is no individual tuning of biasing voltages for individual transistors. Scaled supply voltagescanbe achievedbyscaling thetransistor channel lengths from 1 mm at present (due to the limitations of academic fabrication capa- bilities) to smaller channel lengths1 . Speed. The probe pads and probe card with connecting wires used to connect to the CNT computer add additional capacitive loading to the circuit, limiting the frequency of operation to 1 kHz. However, this is not a fundamental limitation, because commercial chips are packaged and connected to memory and external devices without the use of probe cards, greatly reducing parasitic capacitances. The speed is also limited by the fact that the CNFET gate length is ,1 mm, set by the minimum lithographic feature that can be patterned in our academic clean-room; in field-effect transistors, on-current increases as the gate length decreases1 . Litho- graphicoverlayaccuracyof,200 nmfurtherincreasesparasiticcapacitancesresul- ting in reduced speed. Moreover, the CNT density in this work is ,5 CNTs per micrometre, whereas the target CNT density for increased current drive is 100–200 CNTs per micrometre8 . Several published approaches show promising methods of achieving this target CNT density27 . CNT contact resistance must also be improved for high-performance circuits, and is another source of variation between devices. PMOS-only logic. Logic circuits which use only p-type transistors are known as PMOS-only logic. The design of PMOS-only logic, which is well documented in the literature, is shown in Extended Data Fig. 4. Extended Data Fig. 4a depicts a PMOS-only inverter, whereas Extended Data Fig. 4b depicts a PMOS-only NAND gate. As is apparent from comparison of the two circuits, the pull-down network is always a single p-type transistor, whose gate is biased to remain on continuously. The pull-up network follows the design of typical CMOS circuits. The p-type tran- sistors in the pull-up network create a conducting path from the output to VDD when the output should be logic 1. When the output should be logic 0, the pull-up network is designed to no longer have a conducting path to VDD, and, thus, the single p-type transistor in the pull-down network pulls the output to logic 0. The relative sizing of the pull-up network and pull-down network is critical, because the pull-down network is always biased on. Thus, when the pull-up network should pull the output to logic 1, the pull-down network will still be attempting to pull the output to logic 0. Thus, in our design, the transistors in the pull-up networks are always sized with a width of 10–20 times the pull-down transistor width. Exact transistor sizing is shown in Fig. 3. Multibit arithmetic unit. Additionally, having shown the ability to cascade logic, fabricating a larger multibit CNT computer is not a fundamental obstacle, but rather only affects yield; as a demonstration, we show a two-bit arithmetic unit (composed of 96 CNFETs with a maximum of 15 stages of cascaded logic). The two-bit arithmetic unit is shown in Extended Data Fig. 2. The output waveform tests for all possible inputs, and shows correct operation. Additionally, we show that the circuits regenerate the signal between stages, a necessity for cascading digital logic, by highlighting the noise in the ‘borrow out’ output. Even with noise somewhere within the arithmetic unit (which can have multiple causes: a stage with low swing, electrical noise on the inputs, mobile charges in an oxide and so on), owing to the gain of each stage the final output levels (logic 0 and logic 1) always stay either below or above the threshold for logic 0 or logic 1, respectively (as shown by the horizontal black dotted line). LETTER RESEARCH Macmillan Publishers Limited. All rights reserved©2013
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Extended Data Figure
1 | Fabrication flow for the CNT computer. Steps 1–4 prepare the final substrate for circuit fabrication. Steps 5–8 transfer the CNTs from the quartz wafer (where highly aligned CNTs are grown) to the final SiO2 substrate. Steps 9–11 continue final device fabrication on the final substrate. RESEARCH LETTER Macmillan Publishers Limited. All rights reserved©2013
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Extended Data Figure
2 | Multibit arithmetic unit. a, Schematic of a two-bit arithmetic unit, comprising six individual arithmetic logic units (ALU) as shown in Fig. 3b. b, Measured and expected output waveforms testing all possible input combinations of the two-bit arithmetic unit, showing correct operation. LETTER RESEARCH Macmillan Publishers Limited. All rights reserved©2013
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Extended Data Figure
3 | Internal versus external connections of CNT computer. a, Schematic of the CNT computer, showing that all connections are fabricated on-chip and that only signals reading or writing to or from an external memory are connected off-chip. b, SEM of the CNT computer, showing which connections are made to and from the CNT computer from the probe pads. The SEM is colour-coded to match the coloured wires in a. RESEARCH LETTER Macmillan Publishers Limited. All rights reserved©2013
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Extended Data Figure
4 | PMOS-only logic schematics. a, Schematic of PMOS-only inverter. b, Schematic of PMOS-only NAND gate. LETTER RESEARCH Macmillan Publishers Limited. All rights reserved©2013
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