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Wallace tree multiplier

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Sudhir Kumar
Sudhir Kumar

This document discusses Wallace tree multiplication. It begins by explaining the basic concept of a Wallace tree multiplier using 1-bit full adders to compress the number of bits at each stage. It then provides examples of 6x6 multipliers using Wallace trees. It notes that a 32-bit multiplier using this method would have 9 adder delays. Finally, it asks questions about extending this to a 64-bit multiplier and whether other compression schemes could reduce the delay further.

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National Taiwan University 8.2.7.3 Wallace Tree Multiplication • In effect, a “one’ s counter”: A, B, and C inputs and encodes them on SUM and CARRY outputs. • A 1-bit full adder (FA) provides a 3:2 compression in the number of bits. A. Y. Wu pp. 1
National Taiwan University Ex: 6×6 Multiplier(table) A. Y. Wu pp. 2
National Taiwan University Seven bits Wallace tree addition A. Y. Wu pp. 3
National Taiwan University Ex: 6×6 Wallace Multiplier A. Y. Wu pp. 4
National Taiwan University Example • In a 32-bit multiplier, the maximum number of partial products is 32 and the compressions are： 32 → 22 → 16 → 12 → 8 → 6 → 4 → 3 → 2 =＞ There are 9 adder delays in the array 1. c.f. Array multiplier (Booth-recoded) =16 2. Can be used together with Booth-encoding scheme A. Y. Wu pp. 5
National Taiwan University Wallace Tree Multiplier • MxN Booth-encoded multiplier (IEEE JSSC, vol.1,no.2, June 1993) A. Y. Wu pp. 6
National Taiwan University A typical delay distribution of the output of Wallace tree section A. Y. Wu pp. 7
National Taiwan University Extension • 32-bits Wallace-tree multiplier has 9 adder delays in the array • Questions: 1. For a 64-bit multiplier, what is the minimum adder delay? 2. Is there any way to reduce the delay by other compression scheme? A. Y. Wu pp. 8
National Taiwan University Approach: Using 4：2 compression adder • The 4:2 compression (really 5:3) has three XOR delays in the sum path. • c.f.: Four XOR delays will be present if two adders are used A. Y. Wu pp. 9
National Taiwan University Reference • A 54x54 regularly structured tree multiplier ,IEEE Journal of Solid-State Circuits (vol27 no.9, 1992) A. Y. Wu pp. 10

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Wallace tree multiplier

  • 1. National Taiwan University 8.2.7.3 Wallace Tree Multiplication • In effect, a “one’ s counter”: A, B, and C inputs and encodes them on SUM and CARRY outputs. • A 1-bit full adder (FA) provides a 3:2 compression in the number of bits. A. Y. Wu pp. 1
  • 2. National Taiwan University Ex: 6×6 Multiplier(table) A. Y. Wu pp. 2
  • 3. National Taiwan University Seven bits Wallace tree addition A. Y. Wu pp. 3
  • 4. National Taiwan University Ex: 6×6 Wallace Multiplier A. Y. Wu pp. 4
  • 5. National Taiwan University Example • In a 32-bit multiplier, the maximum number of partial products is 32 and the compressions are： 32 → 22 → 16 → 12 → 8 → 6 → 4 → 3 → 2 =＞ There are 9 adder delays in the array 1. c.f. Array multiplier (Booth-recoded) =16 2. Can be used together with Booth-encoding scheme A. Y. Wu pp. 5
  • 6. National Taiwan University Wallace Tree Multiplier • MxN Booth-encoded multiplier (IEEE JSSC, vol.1,no.2, June 1993) A. Y. Wu pp. 6
  • 7. National Taiwan University A typical delay distribution of the output of Wallace tree section A. Y. Wu pp. 7
  • 8. National Taiwan University Extension • 32-bits Wallace-tree multiplier has 9 adder delays in the array • Questions: 1. For a 64-bit multiplier, what is the minimum adder delay? 2. Is there any way to reduce the delay by other compression scheme? A. Y. Wu pp. 8
  • 9. National Taiwan University Approach: Using 4：2 compression adder • The 4:2 compression (really 5:3) has three XOR delays in the sum path. • c.f.: Four XOR delays will be present if two adders are used A. Y. Wu pp. 9
  • 10. National Taiwan University Reference • A 54x54 regularly structured tree multiplier ,IEEE Journal of Solid-State Circuits (vol27 no.9, 1992) A. Y. Wu pp. 10