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As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non-volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder.

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- 1. Nano Communication Networks 36 (2023) 100454 Contents lists available at ScienceDirect Nano Communication Networks journal homepage: www.elsevier.com/locate/nanocomnet Efficient architecture for arithmetic designs using perpendicular NanoMagnetic Logic Neeraj Kumar Misra a,∗ , Bandan Kumar Bhoi b a School of Electronics Engineering, VIT-AP University, Amaravathi, 522237, Andhra Pradesh, India b Department of Electronics and Telecommunication, Veer Surendra Sai University of Technology, Burla, Sambalpur 768018, Odisha, India a r t i c l e i n f o Article history: Received 28 September 2022 Received in revised form 7 March 2023 Accepted 16 March 2023 Available online 20 March 2023 Keywords: Arithmetic circuit Adder Nanomagnetic logic Nanocomputing Nanotechnology QCA a b s t r a c t As the process of scaling down continues at a rapid pace, there is a growing need for an alternative semiconductor device to replace CMOS. One of the alternatives that attracted a lot of attention is called nanomagnetic logic (NML). This is because NML delivers a high device density in addition to a non- volatility of stored information, beyond-CMOS technologies, and device work at room temperature. It is necessary to lower the circuit density and increase the speed of circuits like adders. Using emerging NML logic, we created a full-adder, and ripple carry adder (RCA) with a minimum area. As a result, the invented multilayer-based decimal design makes use of RCA, and full-adder, for innovative 3D topology. We used an NML framework built with perpendicular nanomagnetic (pNML) layers to simulate the characteristics of these devices. With the adder designs that have been offered the latency values are relatively low while performing exhaustive testing. Using pNML technology, a decimal adder has been constructed for the first time in the literature. In addition, simulations are carried out with the help of the Modelsim simulator. During the process of nanomagnetic designing consideration is given to both of these aspects as latency and area. To create an NML circuit, the tool MagCAD is employed. Results are better using the pNML environment-based full adder, RCA and decimal adder. © 2023 Elsevier B.V. All rights reserved. 1. Introduction Miniaturization is the primary technology that will be applied in manufacturing transistors for high-speed integrated circuits that consume less power [1]. However, the physical boundaries have been reached, and many disadvantages have emerged as a result of the CMOS transistor [2]. These include the short channel effect, limitation of scaling, leakage current, the cost of lithogra- phy, and the propagation delay caused by large capacitance, all of which contribute to an increased effect of uncertainty at the quantum scale [3]. The age in which CMOS technology prevailed may soon come to an end, and with this, a new technology should emerge. It paves the way for many different alternative technologies, such as FinFET, SET, CNT, MTJ, QCA and NML [1]. The perpendicular NanoMagnetic Logic (pNML) technology was viewed as a vital emerging beyond CMOS as well as QCA tech- nology, which ultimately resulted in the insertion of pNML into the pioneering ITRS vision for the latest research devices and the magnetism vision [2]. Both static and dynamic power consump- tion is present in CMOS technology. The status of being shut off is referred to as static power while switching activity is referred to ∗ Corresponding author. E-mail addresses: neeraj.mishra3@gmail.com (N.K. Misra), bkbhoi_etc@vssut.ac.in (B.K. Bhoi). as dynamic power. The amount of power consumed is dependent on the complexity of the circuit; however, if the design is more compact, then the amount of power consumed is significantly lower. There is no possibility of leakage in pNML technology because this technology does not employ transistors but instead relies on magnets to transfer information. If the information flow means only power consumption at that moment in the design, but there is no static power when the system is turned off. NML is considered to be a part of what is referred to as the beyond-CMOS family of technologies, in which the transmission of information is achieved by magneto-dynamic interactions between various devices. The development of quantum-dot cellular automata (QCA) is the driving force behind the CMOS in the market. In QCA, logic operations are carried out by utilizing the coulomb contact that exists between electrons in separate bistable quantum cells [3]. The QCA technology makes use of a high device density and fast processing speed. In addition, QCA technology has promisingly low power consumption during computation, which makes it a viable alternative as an emerging device capable of replacing normal devices. In other words, the QCA technology is capable of replacing conventional CMOS devices [3]. Lent et al. address the fundamentals of QCA-based computing [4]. The QCA technique connects quantum-dot cells by allowing electrons in the cells to interact with one another [5]. The encoding of binary information https://doi.org/10.1016/j.nancom.2023.100454 1878-7789/© 2023 Elsevier B.V. All rights reserved.
- 2. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 in QCA technology is done by two electrons rather than a voltage or current level, which distinguishes it from conventional logic circuits and systems. Operating a QCA device at room tempera- ture is difficult, which is one of its limitations [6]. In addition, the design of fundamental QCA computing elements such as wires, inverter structures, and Logic NAND/NOR gates based on majority voter logic gates for the implementation of many sophisticated devices was proposed in the literature [7]. The most promising aspects of QCA are its lack of interconnects, ultra-high device densities, low levels of power dissipation, and ultra-fast pro- cessing speeds but the main drawback device is not operated at room temperature [8]. It is stated that the QCA computing paradigm might be built in at least one of the quantum physical systems, which include Metal Island, Magnetic, Semiconductor, and Molecular quantum dots [9]. The application of QCA was switched to molecular electronics due to issues in the regularity of cell occupancy, fabrication inconsistencies, and especially the required cryogenic temperature of operation (Molecular QCA) [6]. Tunnelled q-bits are used by QCA to synthesize binary logic bits; this is a technique for transistor-free, current-free, and transient binary logic synthesis that results in a very fast computational speed. This technique for molecular binary logic synthesis works extremely quickly while using very little power [5] The vast majority of contemporary gadgets are built on digital logic, which enables them to carry out digital operations such as arithmetic operations, which include addition, subtraction, multiplications, and divisions, among other mathematical opera- tions [7]. The digital logic system makes use of these fundamental processes to function properly. A digital logic system performs arithmetic operations directly on decimal numbers, and these decimal numbers are represented in the binary-coded form. Nanomagnetic logic, also known as NML technology, is dis- tinguished by several fundamental characteristics, including low- power processing, high device density integration, zero leakage, and device operating at room temperature [8]. In the nanomag- netic logic technique when magnetic orientation is perpendicular to the plane, we designate it pNML, and when it is in-plane we designate it iNML [9]. Compared to iNML, pNML uses far less space and generates significantly less heat, making it one of the most effective NML implementations [10]. The concept of magnetic anisotropy serves as the distinguishing line between the two types of NML Technology [11,12]. These are the parts of the NML that are perpendicular to the plane, also referred to as pNML and in-plane, referred to as (iNML) [13]. MagCAD is a nanomagnetic tool that was developed by ToPoliNano, which stands for TOrinoPOLLItecnico Nanotechnology [8,13,14]. The design of digital logic circuits is the environment of pNML as discussed in [8,15,16]. Designs such as Ex-OR, full adder (FA), ripple carry adder (RCA), and decimal adder in 3D nanomagnetic logic circuits have been completely explored in this article with in-depth analysis. CMOS and QCA technology is being phased out in favour of NML-based digital logic circuits [9,17]. For nanoelec- tronics applications such as adders in pNML, the layout provides a significant benefit in terms of conserving area, magnet count, and latency [10]. In this article, there is a detailed discussion of the synthesis of the full adder, ripple carry adder and decimal adder using 3D nanomagnetic logic. The use of this NML tool for digital logic circuit synthesis such as FA, RCA and decimal adder has been invented in this research work. There was an existing FA design in QCA that could be found in the literature [17–24]. Existing RCA designs that made use of QCA technology might be found in the relevant literature [17,18,20,24–32]. The limitations of QCA devices, their operations can not only be carried out at room temperature [18,19,21–23,33]. Therefore, researchers are looking for an alternative solution to short out the problem described above. After looking through the available research, we find that emerging nanomagnetic logic is the most appropriate method for manufacturing devices at room temperature while making use of nanomagnets [34]. The interaction between the cells that are adjacent to one another is what determines the behaviour of the circuit. The fact that these kinds of devices can be fabricated using technological fabrication procedures that are currently in use is one of the primary advantages of pNML. These kinds of devices can be integrated with normal CMOS, which is another advantage. In addition, nanomagnets can store non-volatile logic information while simultaneously consuming less power than traditional stor- age methods [34]. During the computation, there is no passage of current through the elements. The QCA approach only has one layer, whereas nanomagnetic logic has multiple layers; therefore, using the nanomagnetic technique is the best alternative for reducing the size of the circuit [25,34]. This is the fundamental impetus for our work on the creation of nanomagnetic based adder circuits. This article covers in-depth work on every possible aspect of the design, mathematical expression, simulation, and parameter evaluation using nanomagnetic technology. Ternary logic-based nanocircuit design was implemented in the existing solid research effort highlighted in [35,36]. CLB implementation of FPGA design using emerging QCA technology was discussed in the literature [36]. Compact FA and multiplexer design created using pNML were given in the research published in [37,38]. All of the materials read for the literature review came from these Refs. [20,24,26–32,39–48]. The study work focuses on the many different kinds of adder circuit designs that can be implemented in pNML technology. The non-volatility of NML, operation of the device at room temper- ature, and logic architecture with a minority voter gate are the general characteristics of NML [46]. The pNML offers the fun- damental benefit of shape-independent switching characteristics that may be tuned, in addition to the advantage of directed signal flow. This work demonstrates the use of adder circuits, which are used in digital logic circuits, at the nanoscale by employing opti- mal design and simulation. These invented nanocircuit adders are utilized in nanoelectronics applications. The presentation of the bottom-up approach (Minority voter gate) to the top-level tech- nique (Layout in pNML) and their application in basic computing devices and logic circuits for emerging field coupling devices receives a lot of special attention in this research work. This paper targets FA, RCA and decimal adder architecture for the arithmetic logic circuits using nanomagnetic logic circuit design technique. In this research work, we reduce parameters such as bounded area, latency (the computation delay), and the number of magnets count (device count) in pNML layouts such as Ex-OR, FA, RCA and decimal adder. The lowered cost metrics achieved in the pNML technology layout of the suggested designs, as indicated above, make it particularly appealing for nanoelectronics-related applications. The summary of some of our most important and interesting findings provides support for the claim that our work is novel. • The proposed Ex-OR gate is utilized in the construction of a new Full adder, ripple carry adder and decimal adder layout in pNML technology. • The simulation results of the suggested design, including the FA, RCA, and decimal adder have been successfully con- firmed with the function table. • The implementation of the design for the first completely functional decimal circuit in pNML technology has been analysed, operate at room temperature and introduced in the literature. • The reported pNML parameters such as latency and area, demonstrate that the proposed circuit is more cost-effective in terms of the high-density integration and processing speed of the proposed architectures when compared to conventional circuits in existing work. 2
- 3. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 1. Nanomagnetic logic progression towards a perpendicular nanomagnetic logic (pNML) [46]. • The simulation results of the RCA establish a critical delay of 3.806 µs. • We have presented the robust pNML structure of the deci- mal adder with a critical path delay of only 36 µs. The rest of this paper is organized as follows. In Section 2, an overview of the pNML and decimal adder and related works are presented. A new design, simulation results and performance comparison of design such as FA, RCA, and decimal adder using pNML environment is developed in Section 3. In addition, perfor- mance comparison and MagCAD, a tool for extracting parameters using custom layout editors are present in the same section. The work from Section 4 is given in the section that concludes the paper. 2. The fundamentals of emerging pNML technology Nanomagnetic Logic (NML), which uses the interaction of field-coupled, nonvolatile magnets to execute logic operations, is one intriguing possibility. In this section, the fundamentals of nanomagnetic are introduced, along with a detailed description of their applications. This article makes use of a wide variety of dif- ferent kinds of magnets, which have included some background information about them in advance so that it is easier to read. 2.1. Basic of pNML technology The magnetization orientation of the nanomagnets can either be in-plane (referred to as in-plane Nanomagnetic Logic, or iNML for short), or it can be perpendicular to the plane, depending on the magnetic material that was used (referred to as pNML). The clocking field is a magnetic field that is applied from the outside, and it is this field that allows the nanomagnets to be clocked and switched. In pNML technology, the primary components are the minority voter and the inverter [12]. pNML is distinguished by several key characteristics, including non-volatility, minority gate logic, high device density, energy-aware computing, no reverse leakage, and CMOS-based compatibility [8,34,46]. We have progressed over a brief overview of the historical development of magnetic logic, beginning with its inception in the 1950s through its modern implementation of NML through the use of field-coupled nanomagnets with perpendicular mag- netic anisotropy [48]. This started development with the use of perpendicular magnetic anisotropy (PMA). The amount of study that has been done on Magnetic Logic and the corresponding evolution of pNML [48] may be seen in Fig. 1. In recent years, there has been impressive growth in research on Magnetic logic devices in both iNML and pNML. This is due to the nearing end of the progressive scaling of traditional CMOS technology. Today, the clocking of pNML circuits is implemented by on-chip coils, which use alternating sub- µs field pulses to switch the magnets [48]. These pulses are used to switch the magnets. Because of this, the clocking field serves both as a source of power and as an internal clock. The concept of clocking done on the chip itself is the most significant factor in determining whether or not pNML can be deemed a low-power technology [8,34]. The ‘Domain wall magnet’ is depicted in Fig. 2a. As shown in Fig. 2b, an ‘X-shaped’ magnet is employed to split the input into three separate orientations [13,15]. A ‘corner based’ magnet’ is used to end a magnetic wire, as shown in Fig. 2c. The pNML design of an inverter is shown in Fig. 2d. An inverter is utilized both to invert the signal at the input and to split crucial routes. The input-type magnet is coupled to the output-type magnet in the inverter configuration [14]. An ‘via based magnet’ which is depicted in Fig. 2e. ‘T-type magnet’, ‘corner based magnet’, ‘notch magnet’, ‘pad magnet’, ‘nucleation center’, ‘fixed logic ‘1’ magnet, and pad based magnet are shown in Fig. 2f, g, h, i, j, k, l, respectively. A graphical design of a circuit can be constructed with the MagCAD tool by making use of a variety of various types of mag- nets and keeping the drawing setting’s default parameter intact. Magnet width = 220 nm, Grid size = 300 nm, Interlayer space = 70 nm, and stack thickness = 6.2 nm are the default parameters that are mentioned. Once the layout has been designed using nanomagnet, the next step is to specify the physical parameters, the majority of which involve selecting the default option. Finally, the VHDL code must be generated for simulation operations to be carried out. Our research has made use of the MagCAD tool, which can be found on the ToPoliNano website which in turn stands for TOrinoPOLLItecnico Nanotechnology [49]. This material has covered all of the fundamentals of a decimal adder. A binary-coded decimal (BCD), commonly known as a BCD number, is an encoding that takes a decimal number and converts it into a binary representation using four bits. For adding BCD digits, the BCD adder is utilized. In BCD adder output lie between 0–18. If the total of the binary digits is less than 9, then the binary sum operation will take place. In certain circumstances, if the binary digit is greater than 9, then it needs to be corrected by adding 6 to provide the appropriate outputs. To put it simply, it is a structure that is utilized decimal numbers in digital systems. The decimal adder circuit is one that we favour using when adding decimal numbers in digital systems [11]. A BCD adder 3
- 4. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 2. The modules or basic element in pNML (a) Domain wall magnet (b) X-corner magnet (c) Corner based magnet (d) Logic inverter (e) via based magnet (f) T-type magnet (g) Corner based magnet (h) Notch magnet (i) pad magnet (j) Nucleation center (k) Fixed logic ‘1’ magnet (l) pad based magnet. takes two BCD numbers for addition and results in the same form (i.e. In BCD form). BCD numbers hold a value from 0 to 9 (i.e. 0000 to 1001). While adding two BCD numbers we get output that ranges from 0 to 19 if carry is set to 1 (i.e. 1 + 9 + 9 = 19); otherwise, the maximum output will be 18 if carry is not set (i.e. 0 + 9 + 9 = 18). The addition of two BCD numbers results in a Binary sum that can be converted into BCD with the help of a BCD adder. The result contains 4 bits which can be less than or equal to 9, which means the result is a suitable BCD number. But if the result is more than 9 or if a carry is generated, that means the sum is an invalid BCD number. So to correct the sum, 6 is added to the invalid BCD number as shown in Table 1. When BCD addition takes place either of the below three cases will occur as discussed below: Case 1. If the Sum is less than or equal to 9 with carry out equals to 0 Considering an example as shown in Fig. 3a, when the sum is less than or equal to 9 to carry out equals to 0. The addition of 4 and 5 in BCD is the same as binary addition. Case 2. If the Sum is greater than 9 with carry out equals to 0 The above example, in Fig. 3b, shows when two decimal num- bers 9 and 5 are added which are further written in BCD form i.e. 1001 and 0101 respectively provide a result 14 i.e. 1110. As 14 is an unacceptable BCD number, so to make it an acceptable BCD number 0110 is added to it. When 6 is added to this invalid number a carry is generated in the second decimal position. Now the result 0001 0100 is a valid BCD for 14. Case 3. If the Sum is less than or equal to 9 with carrying out equals to 1 To satisfy this condition BCD of 9 and 8 is taken in addition, as depicted in Fig. 3c, that sum will be generated along with a carry. Binary 00010001 is a BCD number, but the result is incorrect, hence to get a correct result 6 is added. After adding 6 with the incorrect BCD number, 00010111 is the new result. Numbers A and B are both considered to be four-bit digits for this calculation. Because we are working with decimal numbers, the values of A and B can range from 0 (which is equivalent to the binary representation of 0000) to 9 (which is equivalent Table 1 Conversion of Binary sum to BCD sum. Binary sum Sum Decimal Cout X3 X2 X1 X0 Carry S3 S2 S1 S0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 – – – – – – – – – – – 0 1 0 0 1 0 1 0 0 1 9 0 1 0 1 0 1 0 0 0 0 10 0 1 0 1 1 1 0 0 0 1 11 0 1 1 0 0 1 0 0 1 0 12 0 1 1 0 1 1 0 0 1 1 13 0 1 1 1 0 1 0 1 0 0 14 0 1 1 1 1 1 0 1 0 1 15 1 0 0 0 0 1 0 1 1 0 16 1 0 0 0 1 1 0 1 1 1 17 1 0 0 1 0 1 1 0 0 0 18 1 0 0 1 1 1 1 0 0 1 19 to the binary representation of 1001), and the output can range anywhere from 0 to 18 if the carry from the previous sum is ignored. However, if the carry is taken into consideration, the highest possible output value is 19 (that is, 9 plus 9 plus 1 equals 19). Because each decimal digit must be represented by 4 bits, a decimal adder must have a minimum of 9 inputs and 5 outputs, as well as an input Cin and an output carry Cout. Additionally, it must have a carry input and carry output. The BCD correction is examined through a logic circuit that is determined by the existence of binary numbers from 1010(10) to 10011(19) as an output of the binary adder. The correction is also required when output carry is generated, this state occurs when the sum is equal to sixteen or greater than 16. A BCD adder circuit consists of two four-bit ripple carry adder and a correction circuit. Two decimal inputs of 4-bit each are added together with the previous input carry, to generate a binary sum. The stipulation for correction can be stated by the Boolean expression. From Table 1, we can analyse the logic when we add 0110 to the binary sum. We have discussed the 3 cases as follows: 4
- 5. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 3. BCD operations using digital bits (a) Sum < 9 and Carry = 0 (b) Sum > 9 and Carry = 0 (d) Sum > 9 and Carry = 1. Fig. 4. K-map for BCD adder. The cases are 1. If Cout = 1 (that occurs at 16–19) 2. If X3.X2 = 1 (that Satisfies 12–15) 3. If X3.X1 = 1 (that Satisfies 10 and 11) To form a logic from the above three cases we have used Karnaugh-map as depicted in Fig. 4. Here we have used 4 variable k-map in SOP form. So from the k-map we get X3.X2 + X1.X0 as a result and we have already observed from Table 1 that if Cout = 1 then Z will become 1. So the final expression for the correcting Binary output to BCD is Cout + X3.X2 + X3.X1 = 1 (It is equal to carry Z) This can be easily achieved by a correction circuit, which con- sists of two AND and two OR. The output of this correction circuit is represented by Z as shown in Fig. 5. The above expression shows that whenever Z is set to 1 then only 0110 will be added to the binary sum. To satisfy the above condition again a four-bit ripple carry adder is used, which takes two 4-bit inputs. So one of the 4-bit inputs is the sum of binary adders and the other 4-bit input is 0110 which can be accomplished by connecting Z to the input at a binary weighted position of 2^1(2 to the power 1) and 2^2(2 to the power 2) and other two-bit position is provided to 0. 3. The proposed pNML layout In Section 3.1, we suggested using the Ex-OR gate when de- signing the RCA, and decimal adder. This block of Ex-OR gate is utilized to synthesize the FA, RCA, and decimal adder. 3.1. The new design of Ex-OR gate The Ex-OR operation is carried out by combining ordinary logic gates to build more complicated gate functions. These more com- plex gate functions find widespread application in the creation of arithmetic logic circuits, computational logic comparators, and error detection circuits [16]. The block diagram of Ex-OR gate is depicted in Fig. 6a. In Fig. 6b depicts a minority voter schematic diagram, while Fig. 6c depicts a pNML arrangement. Minority gate is represented by Min. The outcomes of Exclusive OR expressions using minority voters are shown in Fig. 7. The output equation is shown in Eq. (1) O = (M4 (M2 (A, 0, M1(A, 0, B)) , 0, M3 (B, 0, M1(A, 0, B)))) (1) = M4 (M2 (A, 0, M1(A, 0, B)) , 0, M3 (B, 0, M1(A, 0, B))) = M4(M2 ( A, 0, AB ) , 0, M3(B, 0, AB)) = M4(A.AB, 0, B.AB) = ( A.AB ) .(B.AB) = AB + AB Because the magnetic wires are separated into their layers, the proposed architecture is a three-dimensional circuit (3D0). Because, according to the concept of nanomagnetism, an input made in one layer is transported and reversed into another layer, we can flip the direction of an input simply by switching which layer it is made in. Both of the circuit’s inputs, A and B, have to be connected to the ‘0’ layer for there to be any chance of getting the output 0. The NAND gate will be triggered if any of the inputs from the minority voter are ‘‘0’’, since the phenomenon of perpendicular nanomagnets suggests that this will happen if any of the inputs from the minority voter are ‘‘0’’. An inverter and four minority voters are used in combination with the construction of an XOR gate as a direct consequence of this fact. Fig. 6 depicts the configuration of the Exclusive OR gate that was modelled as a consequence of the simulation. As a consequence of this, the design that was suggested satisfies the truth table requirements for the Exclusive OR gate. The bounding box space that the total design occupies is 9.72 µm2 . 3.2. One-bit full adder design proposed in pNML technology In Fig. 8a shows a FA implementation employing two AND gates, two Ex-OR gates, and one OR gate. It has three inputs: A, 5
- 6. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 5. Block view of decimal adder. B, and C, as well as two outputs: Sum and Cout, as shown in Eqs. (2) and (3). Sum = A xor B xor C (2) Cout = AB + BC + CA (3) Fig. 8b depicts a main full adder with a minority voter. The creation of a platform for a three-input, two primarily output sum and Carry is intended to be the result of this design’s efforts. To make the calculation easier, we have express equations in terms of minority voter gate as depicted in Eqs. (4) and (5). S = M8(M6(X, 0, M5(X, 0, C)), 0, M7(M5 (X, 0, C) , 0, C)) (4) = M8(M6(X, 0, X.C), 0, M7(X.C, 0, C)) = M8(X.XC, 0, XC.C) = (X.XC.XC.C) = X.XC + XC.C = XC(X + C) = (X + C)(X + C) = X.C + C.X = ABC + ABC + ABC + ABC Cout = M10(M9 (C, 0, M4 (M2 (A, 0, M1 (A, 0, B)) , 0, (M3 (B, 0, M1 (A, 0, B))))), 1, M1(A, 0, B)) = M10(M9 ( C, 0, M4 ( M2 ( A, 0, AB )) , 0, M3 ( B, 0, AB )) , 1, AB) = M10 ( M9 ( C, 0, M4(A.AB,0, B.AB) ) , 1, AB ) = M10(M9 ( C, 0, AB + AB ) , 1, AB) = M10(C. ( AB + AB ) , 1, AB) = M10(C. ( AB + AB ) , 1, AB) = C. ( AB + AB ) + AB = AB + BC + CA (5) A Full-adder in pNML environment is utilizing 10 minority voters and 2 inverter gates, as shown in Fig. 8b. The behaviour of the design looks like with fixed 0 inputs, all minority voter designs behave like NAND logic gates and fixed 1 input, all minority voter designs behave like a NOR logic gate. The design below uses a 45.9 µm2 bounding box area. It has a 2.5 µs critical route delay. The complete layout in pNML technology is depicted in Fig. 8c. The timing results obtained via exhaustive testing (every pos- sible combination) of varied inputs circumstances have provided evidence that the functioning behaviour of the NML circuit has been demonstrated. Fig. 9 summarizes the results that were ob- tained by simulating a one-bit Full Adder. The circuit provides output S as 0 and Cout as 0 with a delay of 2.4 us, when the input nodes A, B, and C are all zero. If A = 0, B = 0, and C = 1, we get S = 1 and Cout = 0 with a delay of 2.5 µs; if A = 0, B = 1 and C = 0, the circuit produces S = 1 and Cout = 0 with a latency of 2.4 µs; and if A = 0, B = 1 and C = 1, we get S = 0 and Cout = 1 with a latency of 2.4 µs. Table 2 lists all of the characteristics of the proposed layout as well as the delays for 6
- 7. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 6. Design of Ex-OR (a) Block design (b) Minority gate based design (c) 3D layout. Fig. 7. Simulation result of the pNML layout of Exclusive OR gate. various input combinations. The calculated area of 45.9 µm2 of the new architecture full adder is very less. As can be seen from the results obtained during the simulation and shown in Table 2, the simulated input condition of (1, 0, 0) has the longest delay. The longest delay is considered the critical delay. The application of QCA to magnetic materials in the form of Magnetic Quantum Cellular Automata (MQCA) in the year 2000 was a significant advancement for QCA and marked the beginning of NML [46]. Due to the coming end of the progressive scaling of conventional CMOS technology, research on magnetic Logic devices has seen an astonishing surge in both iNML and pNML over the past few years. This increase can be attributed to the fact that. During the process of analysing Magnetic Logic devices, the investigation of Quantum Cellular Automata will be carried 7
- 8. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 8. Design of 1-bit full adder (a) block diagram (b) pNML schematic (c) 3-D pNML layout. out (QCA). The so-called ‘‘clocking field’’ is a magnetic field that is applied from the outside, and it is this field that allows the nanomagnets to be clocked and switched [46]. As a result, to compare performance, in our work, we have taken into account both QCA and NML. This is because advancements in QCA are referred to as NML. It is shown that the proposed FA design requires 3.5 clock cycle to carry out and has a lower level of complexity in terms of magnet field computation, as shown in Table 3 when compared to other strategies that are comparable such as QCA and NML. The following is an advantage that we have in the existing designs of the FA work [8]. In the existing designs [8] of the FA, 8
- 9. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 9. The result on the proposed layout of a 1-bit full adder. Table 2 Performance table proposed of 1-bit full adder. Critical path = 3 µs Bounded box area = 45.9 µm2 Inputs Outputs Latency A B C S C 0 0 0 0 0 2.4 µs 0 0 1 1 0 2.5 µs 0 1 0 1 0 2.4 µs 0 1 1 0 1 2.4 µs 1 0 0 1 0 3 µs 1 0 1 0 1 2.4 µs 1 1 0 0 1 2.5 µs 1 1 1 1 1 2.4 µs all of the inputs, A, B, and C, were treated as if they were inverted to calculate the right output. With the inputs being inverted like this, the FA design requires more magnets. In the synthesis process, an increase in the magnet will result in a rise in both the area and the clock cycle. This is the primary limitation in the FA design of the work that has already been done. However, in our research and design of FA, normal input is used, and we use fewer inverters and magnets than in other designs. This has the advantage of reducing the amount of space required for the calculation while also boosting its overall speed. The FA design process is the invention that is being discussed below. In the design of FA, we used an inter-magnet space of 70, whereas the existing work [8] that was done previously used inter-magnet space of 150. If there is a smaller distance between adjacent magnets, the design will be more compact, and the field coupling will be stronger, which will result in a more efficient computational process. As a result of this, the invented FA has an optimal minimum clock period of 300 ns, whereas the work done in the present [8] takes 1570 ns. This indicates that by making use of the standard inter-magnet space, we will achieve a better valuation of the clock period. This exemplifies the quality of the work that we produce. The suggested design of FA has only 3.5 clock cycle, whereas the existing system has 4 clock cycles. All of these factors as discussed above indicate that the work that is being proposed is an improvement over the work that is already being done [8]. 3.3. The proposed ripple carry adder layout in pNML technology The construction of a four-bit ripple carry adder is accom- plished by cascading and connecting in series four full adder circuits. The carry-in and carry-out of the full adder are associated with each stage because they are located next to one another. Ripple carry adder is one of the example of Binary Adder. A binary adder is used to achieve a Binary sum as a result of the addition of two binary numbers [34]. Normally in 1-bit full adder, there is three inputs and two outputs sum and carry. In the ripple carry adder, four 1-bit full adders are placed adjacently and generated carry of the first full adder is fed to one of the inputs of the next 1- bit full adder, this process is carried out till the last full adder. So, the final carry is taken from the last full adder and four sums from each stage will be the overall sum of two binary numbers [25]. Hence, a four-bit ripple carry adder have two inputs each of four- bits and two outputs a sum which is of 4-bit and a carry. So another name for this ripple carry adder is pseudo parallel adder or simply a parallel adder. Always the first full adder is observed as LSB and the result from this full adder is taken as LSB bit of sum. Likewise, the last full adder is considered as MSB and results from this full adder is taken as MSB bit of sum. The block view of RCA is depicted in Fig. 10. In Fig. 10, the ripple-carry-adder is constituted by four 1-bit full adders. The full-adder1 provides LSB bit of sum (i.e. SUM0) and the MSB bit of sum is taken from FA_4. CIN is the carry-in of fulladder1, which is initialized to 0. Fulladder4 holds the value of the final carryout. The proposed pNML layout of four-bit RCA is represented in Fig. 11. This design has been implemented in two different layers (layer_0 and layer_1). The blue colour represents layer_0 and the yellow colour represents layer_1. Whenever colour changes from one layer to other, it means the signal is complemented. Four-bit, two binary number A & B are taken for addition (i.e. A3, A2, A1, A0 & B3, B2, B1, B0). The binary bits of both A & B at position 2 to the power zero is provided as input to the last full adder and the third input C0 is initialized to 0. The output such as the sum from full adder i.e. S0 is taken as the LSB bit of the binary sum and the other output carry is connected to one of the inputs of the next full adder. The pNML circuit of a 1-bit full adder is used, which is already mentioned in the previous Section 3.2. The carry-out of this full adder is in layer_1 and input of next full adder is in layer_0; to make a connection between these two an inverter is used, so that it may not complement the signal which results from the first full adder. Likewise, the rest of the full adder is being connected. Hence the last full adder gives the final carry. The sum from each full adder is taken and placed at their respective bit position to form a binary sum (S3, S2, S1, S0). The complete layout of the ripple carry adder is depicted in Fig. 11. After the designing of the pNML layout has been finished in the MagCAD tool, an automatic VHDL file will be generated. This file contains information about the area that is covered in the designing of the layout, and it also contains some code related to library files, about the behaviour of the circuit, entity, and definition of each element used in it. In addition, this file contains information about the area that is covered in the design of the layout. Therefore, this code is what is utilized to construct the test bench for the circuit that is depicted in Fig. 12. Table 4 shows the performance of the proposed four-bit Ripple carry adder. Here An and Bn are the inputs where n represents the bit positions. C0 is the initial carry i.e set to 0. The notation Cn is the output carry and Sn is the sum which is produced after the addition operation. The blue colour arrow shows after performing each addition operation Con will become Cn for the next. The last column shows latency in microseconds as depicted 9
- 10. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Table 3 The performance table of the FA. Designs of FA Latency Area in µm2 Technology used Single/multilayer Operate at room Temp (Yes/No) Ref [17] 1.25 0.09 QCA Single-layer No Ref [18] 1.25 0.06 QCA Single-layer No Ref [19] 0.75 0.03 QCA Single-layer No Ref [33] 0.75 0.04 QCA Single-layer No Ref [21] 1 0.07 QCA Single-layer No Ref [22] 0.75 0.04 QCA Single-layer No Ref [23] 1 0.04 QCA Single-layer No Ref [24] 2 0.009 QCA Single-layer No Ref [44] 2.5 0.26 QCA Single-layer No Ref [8] 4 clock cycle 49 NML Multi-layer Yes New FA design 3.5 clock cycle 45.9 NML Multi-layer Yes Fig. 10. Block view of four-bit ripple carry adder. Fig. 11. The suggested three-dimensional pNML layout of the 4-bit RCA. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.) in Table 4. The critical path for this circuit is 3.806 µs. The overall area covered in the ripple carry-adder is 283.59 µm2 . The proposed 4-bit ripple carry adder layout in pNML is shown in Fig. 11 and it was compared with the existing work in the literature as per [8,17,18,20,24–32,44,45] and shown in Table 5. The new architectures show many primitives in terms of latency and bounded area allowing the implementation of complex logic functions related to arithmetic circuits (see Table 6). 3.4. The proposed pNML design of decimal adder A decimal adder encompasses two RCA, two 2-input AND gate, and two 2-input OR gate. In the construction of the correction circuit, it is important to have two 2-input AND gates and two 2-input OR gates. RCA has been already proposed in Section 3.3. Fig. 13 shows the pNML layout of the decimal adder. Using minority voter AND, OR gate has been implemented. To make an AND gate using a minority voter, one of its inputs is fixed to 0, likewise to make an OR gate using a minority voter, one of its inputs is fixed to 1. The RCA has two 4-bit inputs. The first input is a four-bit binary sum, which is obtained from the first RCA. The other input is six (0110), hence Y3 and Y0 are connected to the FA, which is placed at the first and last position so that at the time of generating the test bench zero will be directly provided to it; and for getting rest two bits, input is followed by some AND and OR gates. When both the sum (S3, S2) or sum (S3, S1) or carry from the first ripple carry adder is 1, then only six will appear at the input of the second RCA. Otherwise, the result will be the 10
- 11. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 12. Simulation outcomes of 4-bit RCA. Table 4 The performance table of the 4-bit RCA. Table 5 Comparison results of the 4-bit RCA. Designs Latency Area (In µm2 ) Technology used Single or multilayer Operate at room Temp (Yes/No) Ref [17] 4.25 0.68 QCA Single-layer No Ref [18] 2 1 QCA Single-layer No Ref [25] 1.25 0.3 QCA Single-layer No Ref [26] 3.25 2.5 QCA Single-layer No Ref [27] 3.5 0.37 QCA Single-layer No Ref [20] 2 0.29 QCA Single-layer No Ref [28] 1.75 0.208 QCA Single-layer No Ref [29] 1.5 0.24 QCA Single-layer No Ref [30] 1.5 0.3 QCA Single-layer No Ref [31] 1 0.14 QCA Single-layer No Ref [24] 5 0.18 QCA Single-layer No Ref [32] 3.75 0.12 QCA Single-layer No Ref [44] 10 6.01 QCA Single-layer No Ref [45] 2.75 0.17 QCA Single-layer No New RCA (4-bit size) 14 clock cycle 283.59 NML Multilayer Yes same as engendered by the first RCA, because a 4-bit zero will be added to the binary sum. Final carry is ignored which has been generated at the end of all operations from the second RCA. The bounding box area of the circuit shown in Fig. 13 is 823.68 µm2 . Two inputs A and B are associated with the decimal adder, each provided by 4 bits. The 4-bit A and B are added through a decimal adder. In this case, if we get 1110 as a result of sum and 0 as a carry (i.e. cout = 0). Since the result is greater than 9, so to convert it into decimal 0110 is added to it. As we have seen a correction logic, if z is set to 1 then 6 will be automatically added to the binary result. Hence the final result of the decimal adder is 0100 (S3 S2 S1 S0) and 1 as a carry. The simulation time to get the carry of the binary sum is 36 µs. Fig. 14 shows the simulation result of the decimal adder, so the simulation time to get S0 is 36 µs. The simulation time of S1 and S2 depends upon inputs as well as the output of the correction circuit. Bit S3 will be generated at 36 µs. Therefore, the critical path of the circuit is 36 µs. 3.5. MagCAD, tool for extracting parameters using custom layout editors We have covered in this section how the Verilog netlist is generated from the MagCAD tool. In pNML, the antiferromagnetic field coupling that occurs between nearby magnets makes it possible for just two magnets to interact to flip the direction of the magnetization from input to output [12]. By simply severing the magnetic nanowire into various branches, it is possible to easily realize the fanout structures that are required to drive several gates using only a single output [15,16,34,46]. Support for the intricate digital logic structures is provided by pNML. Fig. 15 contains a listing of all of the default parameters for the custom 11
- 12. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 13. Proposed 3D pNML layout of decimal adder. Fig. 14. The outcome of the decimal adder. Table 6 Results of the comparison using the decimal adder. Designs Latency Area (In µm2 ) Technology used Single or multilayer Operate at room Temp (Yes/No) Ref [40] 2.50 1.86 QCA Single layer No Ref [41] 8 2.28 QCA Single layer No Ref [42] 26 6.68 QCA Single layer No Ref [43] 86 17.48 QCA Single layer No New decimal adder 30 clock cycle 823.68 NML Multilayer Yes 12
- 13. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 Fig. 15. pNML default parameters. Fig. 16. VHDL physical parameter choice. layout using pNML technology. The minority voter and the in- verter are the fundamental constituents that make up the pNML technology [50]. When the design phase of the circuit is finished, MagCAD will generate VHDL physical parameters choice, along with a Verilog netlist and a technology definition as depicted in Fig. 16. The Verilog code for the circuit can be exported after it has been automatically generated by MagCAD. When the netlist is extracted, each of the components in the layout is read as a unique element in the net-list form. The results of simulations can be acquired by using simulators like Xilinx Vivado Design Suite 2022.2.1. In addition to this, we compute parameters such as the latency and the area of the bounding box. The temperature used in all the simulations is 293K0. When simulation of QCA design is carried out at room temperature, in QCA output nodes 13
- 14. N.K. Misra and B.K. Bhoi Nano Communication Networks 36 (2023) 100454 polarization is significantly reduced. Compared to QCA design, nanomagnetic logic can function at ambient temperature, which is a major benefit. That means that suggested adders design in pNML-based nanomagnetic logic has the potential to have an impact on the research that is being done right now. 4. Conclusion and future scope As the limitations of scalability in MOS transistors become in- creasingly apparent, there is a growing need for alternative tech- nologies. Researchers have shown a significant amount of interest in the potential alternative technology known as nanomagnetic logic. The key factor that is driving the creation of new research parameters for high-speed logic architectures is the decrease in circuit density as well as the increase in processing speed. To develop nanomagnetic logic circuits, such as FA, RCA, and decimal adders for use in arithmetic logic circuits, we make use of a new method that is based on nanotechnology. In this article, compact nanocircuit architecture is invented. Some proposed designs, such as the FA, RCA, and Decimal adder, require only a small number of magnets and high-speed logic bit processing. In addition to this, the new Ex-OR gate was used in the construction of NML circuits. The suggested RCA has a 283.59 µm2 area. The suggested decimal adder has an area of 823.68 µm2 . The new architecture features impressive levels of optimization in terms of area and total latency, which makes it possible to use the MagCAD tool to design nanomagnetic logic operations. The current study shows that pNML meets and even surpasses the criteria for upcoming beyond-CMOS devices, making it a viable emerging device can- didate for hybrid CMOS/pNML integrated circuits. In the future, look into more various methods for manufacturing things so that pNML devices can be made as cheaply as possible. CRediT authorship contribution statement Neeraj Kumar Misra: Conceptualization, Visualization, project administration, Funding acquisition, Formal analysis, Methodol- ogy, validation, supervision, Writing – original draft, Writing – review & editing. Bandan Kumar Bhoi: Visualization, Funding acquisition, validation, Formal analysis, Methodology, Writing – original draft, Writing – review & editing. Declaration of competing interest The authors declare that they have no known competing finan- cial interests or personal relationships that could have appeared to influence the work reported in this paper. Data availability No data was used for the research described in the article Funding Not applicable. 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[50] Moein Kianpour, Reza Sabbaghi-Nadooshan, A conventional design for CLB implementation of a FPGA in quantum-dot cellular automata (QCA), in: Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012, pp. 36–42. Dr. Neeraj Kumar Misra is an Associate Professor at Vellore Institute of Technology (VIT) -AP University Amaravati, India. He has more than 9 year experience in teaching and research. He is the Senior Member in IEEE. He did his Full-time Ph.D under the Teach- ing Education Quality Improvement Program (TEQIP-II), Government of India and a World Bank Fellowship from Dr. A.P.J. Abdul Kalam Technical University in the year 2017. He did his B.Tech from Integral University, and his Post-Graduation first class with distinction. He did PGD in Machine Learning & Artificial Intelligence from NIT Warangal. He has received a funded FDP grant from AICTE-ISTE INDUCTION/REFRESHER PROGRAMMES. titled ‘‘Pedagogy: Innovative Methods of Teaching and Learning’’ as single Coordinator. He is the inventor or co- inventor of 7 Indian patents published and 3 international patents granted. He is the author or a co-author of more than 50 papers published in SCI, Scopus, and peer-reviewed international journals, and conference proceedings. He has published 14-SCI papers in Springer, Elsevier, World Scientific, Taylor & Francis, Wiley, and IET, and a 15-Book Chapter in Springer. He is the author or a co- author of 3 international books. The paper with the highest impact factor, 8.907, was published in Elsevier’s Journal of Energy Storage. Under his supervision 14 M.Tech (Completed) and 3 Ph.D (Ongoing) students completed degree. He has received the best paper award in National Conference on Advancement in signal processing & Integrated Networks (SPIN) at Amity University, Noida in the year 2011 and Best paper award in Springer sponsored International Conference on Micro/Nanoelectronics Devices, Circuits, and Systems at NIT Silchar, Assam, India in the year 2022. He has a professional member of ISTE, ACM, IAENG, IEEE, IRED, World Research Council, and IETE etc. His research interest is in Quantum computing, reversible computing, Fault-Tolerant Circuit Architecture, QCA technology, Nano-magnetic logic, DFT, and Low Power and Reliability-Aware VLSI circuits. Dr. Bandan Bhoi received his Ph.D. from Veer Surendra Sai University of Technology, India; an M.Tech degree from IIIT Hyderabad, India; and a B.Tech in ECE from Biju Patnaik University of Technology, India. He worked as a design engineer in the VLSI industry from 2010 to 2011. He is working as an assistant professor in ECE at Veer Surendra Sai University of Technology, India. He has granted two Australian International Patents re- lated to Quantum computing (Patent no. 2020103849, and Patent no. 2020102068). His research areas in- clude Reversible Computation, QCA, and reconfigurable computing architectures. 15