1. Introduction to
Phase Locked Loop
(PLL)
DIGITAVID, Inc.
Ahmed Abu-Hajar, Ph.D.
abuhajar@digitavid.net

2. Presentation Outline
What is Phase Locked Loop (PLL)
Basic PLL System
Problem of Lock Acquisition
Phase/Frequency Detector (PFD)
Charge Pump PLL
Application of PLL

3. What is Phase Locked Loop (PLL)
PLL is an Electronic Module (Circuit) that
locks the phase of the output to the input.
Vi(t) Phase Locked
Vo(t)
Loop

4. Locked Vs. Unlocked Phase
Example of locked phase
Vi(t)
Vo(t)
Example of unlocked phase
Vo(t)
Vi(t)
Phase Error
( )

5. Basic PLL System
PLL is a feedback system that detects the phase error
and then adjusts the phase of the output.
Vi(t) Vo(t)
The Phase Detector (PD), detects between the output
and the input through feedback system
Voltage Control Oscillator (VCO) adjusts the phase
difference
Phase Locked
Loop
Phase
Detector
VCO Vo
VI

6. Implementation of PD
Phase Detector is an XOR gate
Phase
Detector
VCO Vo
VI
V 1
Vo
1
0
V V
I o
V V
I o
j
¹
D =
=
Vo(t)
Vi(t)
Phase Error
( )

7. What is VCO ?
VCO is a circuit module that oscillates at a
controlled frequency .
The Oscillating Frequency is controlled using
Voltage VControl.
– That is why the module is called
Voltage Control Oscillator
VControl
VCO
w =w + K V
Vcontrol must be in the steady state for the VCO to
operate properly
0
VControl
o VCO Control

8. Simple PLL
Structure
– Phase Detector ( XOR ) that detects the phase error
– Low Pass Filter ( to smooth )
– Voltage Control Oscillator (VCO)
Basic Idea
– If VI and Vout are out of phase (unlocked), then the PD module
detects the error and the LPF smoothes the error signal. The
control signal slows down or speeds up the VCO module; hence,
the phase is corrected (locked)
Phase Vout
VCO
Detector
VI
Vout
LPF VControl

9. Locked Condition
– Locked Condition
( ) 0 in out
– This implies that
Phase Vout
VCO
Detector
VI
Vout
LPF VControl
d
dt
j −j =
in out w =w

10. Example: In the UNLOCKED State
VI and Vout has at the same
frequency 1
The phase detector must
produce VI
Hence, VCO is dynamically
changing and PD is creating
VControl to adjust for the phase
difference.
The PLL is in the Locked state
Vi(t)
Vo(t)
Phase Error
( )
VControl
1
0
VControl
V1
VControl
V1
0

11. In the UNLOCKED State
For Simplicity and by using Fourier Series
Let
V =V w t ( ) 1 cos out B o
( ) 1 cos I A
V =V w t +j
Due to , PD creates Vcontrol
VCO will change
w =w + K V
out 1 VCO Control
The output voltage becomes
( ) 1 cos ( ) out B o
V =V w t +j − Dj t

12. Dynamics of Simple PLL
PLL is a feedback system
– PD is a gain amplifier
– LPF be first order filter ( as an example)
– VCO is a unit step module
The transfer function of the feedback system is given as:
w w
w Vw w
F
= = =
out out n
H s s s
F + + 2
PD
VCO
s s
LPF
in K
out KVCO
PD
s
1
1
s
w
LPF
+
2
2 2
( ) ( ) ( )
2
in in n n
K K
w
( ) PD VCO LPF
w w
LPF PD VCO LPF
H s
s s K K
=
+ +

13. Transient Response to PLL
The unit step response to second order system
– Overdamped
– Critically damped
– Underdamped
Problems with this PLL
– Settling time Vs. ripple of Vcontor
– Stability of the system
– Lacks performance in ICs
F
= = =
w w
w Vw w
out out n
H s s s
F + +
PD
s s
VCO
LPF
in K
out KVCO
PD
s
1
1
s
w
LPF
+
2
2 2
( ) ( ) ( )
2
in in n n
t
i
out
t

14. Problem of Lock Acquisition
When PLL is turned on, the output frequency is far from
the input frequency
It is possible that the PLL would never lock
Modern PLL uses FREQUENCY DEDECTOR (FD) in
addition to the PD.
VCO
LPF1
LPF2
PD
FD
Vout
out
Vin
in

15. Phase/Frequency Detector (PFD)
One Module that detects both frequency and phase differences
This module senses the transition in A or B
A B QA QB
Initially 0 0 0 0
A leads B 0 1 0 0 0 1 0 0
XX 0 1 1 0 0 0
A B QA QB
Initially 0 0 0 0
B leads A 0 0 0 1 0 0 0 1
0 1 XX 0 0 0 0
A PFD
B
If A leads B, QA changes its state and QB remains unchanged
If B leads A, QB changes its state and QA remains unchanged
QA
QB
A
B
QB
QA
A
B
QB
QA

16. Hardware Implementation of PFD
Uses two Edge Triggering modules
using D-FF
If A leads to “1” QA = “1”
– When B becomes “1”, QB = “1”
momentarily
– The AND gate RESETs Both to Qs “0”
If B leads to “1” QB = “1”
– When A becomes “1”, QA = “1”
momentarily
– The AND gate RESETs Both to Qs “0”
VDD
A
QA
QB
D
CK
Q
D
CK
Q
VDD
B

17. Hardware Implementation of PFD
VDD
A
QA
QB
D
CK
Q
D
CK
Q
VDD
B
RES
A
B
QB
QA
RES
A
B
QB
QA
RES
The Vout is the average of (QA – QB)
is used to detect the phase and the
frequency difference

18. The Basic Block diagram
Structure
– PFD
– LPF
– Differential
Amplifier
– VCO
– Negative Feedback
Disadvantage:
Sensitive to noise
and offset voltages,
ripple Vcontrol, ..
Use Charge Pump
PLL
D
CK
Q
D
CK
Q
VDD
Vin
in
in
VDD
QA
QB
Vout
out
out
VCO

19. Charge Pump PLL
Structure
– PFD
– Two switches
controlled by QA
and QB
– Capacitor
dV
=
I C
d t
dV I
=
– VCO
– Negative Feedback
– It charges or
discharges the
capacitor
indefinitely
D
CK
Q
D
CK
Q
VDD
Vin
in
in
VDD
QA
QB
Vout
out
out
VCO
VDD
C
C
C C
d t C

20. Charge Pump PLL
The capacitor is replaced
with a LPF (Cp and Rp) to
improve the phase margin
for stability
The transfer function of the
system is approximated as
follows:
P VCO
P P
P
+
P P VCO
VCO P VCO
Rp slows down the system
D
CK
Q
D
CK
Q
VDD
Vin
in
in
VDD
QA
QB
Vout
out
out
VCO
VDD
CP
RP
( )
2
1
2
( )
2 2
P
I K
R C s
C
H s
I I K
s K R s K
C
p
p p
=
+ +

21. Application of PLL
Frequency Multiplications
– The feedback loop has frequency division
– Frequency division is implemented using a counter
Clock Skew Reduction
PFD Vout
Buffers are used to distribute
the clock
Embed the buffer within the loop
VCO
VI
LPF VControl
Counter
(Frequency
Division)

22. Application of PLL
Clock Skew Reduction
– Buffers are used to distribute the clock
– Embed the buffer within the loop
PFD Vout
Jitter Reduction
VCO
VI
Vout
LPF VControl
Buffer