Wearable Technology applications are by definition portable, battery powered and very concerned about power consumption, analog performance and cost. Triad Semiconductor makes Reconfigurable Mixed Signal ASICs ( rASIC (tm) ) that help wearable tech companies get products to market quickly and inexpensively. This presentation shows the ultra low power and precision analog performance that can be crafted in a Triad rASIC.
2. Low Cost Mixed Signal ASIC Design
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Triad Semiconductor
Reconfigurable ASIC Solutions
Triad Semiconductor, www.TriadSemi.com, designs and manufactures
Reconfigurable Mixed Signal ASIC solutions known as rASICs™.
An rASIC™ is a full-custom mixed signal ASIC designed to your
specification. Your rASIC can be reconfigured with a single via mask
change using Triad’s patented via configurable technology.
rASIC benefits include
• Full-custom mixed signal ASIC performance & unit cost.
• 50% faster time to market verses traditional ASICs.
• 70% savings in development costs.
• Complete IP protection – your rASIC cannot be copied or cloned by
your competitors and your rASIC cannot be purchased by others.
3. Low Cost Mixed Signal ASIC Design
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Introduction
This presentation provides an analysis of the power consumption
of a mixed signal circuit implemented on a Triad rASIC.
Assumptions
• This is a case study for a wearable sensor device
• The device is battery powered
• Size, Weight and Power reduction is critical
• Extensive optimization to each aspect of the ASIC design will
be performed to reliably meet the performance goals of the
product and yield the lowest power design possible.
4. Low Cost Mixed Signal ASIC Design
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Attribute Comparison of Triad’s rASIC and a
Traditional Full-Custom ASIC
Note 1: Discrete development cost assumes two
engineers @ $150K/year burdened cost supporting the
project for one year. Triad’s rASIC cost is an all inclusive
charge for the turnkey development of a custom rASIC.
Attribute Catalog IC Design Triad rASIC
Traditional
Full-Custom ASIC
Development Cost $300,0001 $300,000 $1,000,000+
Development Time 2-9 months 6-9 months 18-24 months
Re-spin time 1-4 weeks 4-6 weeks 20-24 weeks
Analog Performance Fair
Full-custom
optimized
Full-custom
optimized
Power Consumption
in general
Not Fully
Optimized
Full-custom
optimized
Full-custom
optimized
Power Consumption
this example ~1000uA 216 uA 216 uA
Electronic Design Engineers spend 10-35% of
the design cycle doing component selection, with
Triad rASIC, each component is customized to
Spec in the same amount time.
5. Low Cost Mixed Signal ASIC Design
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Target Block Diagram
8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
• Device measures Air Quality,
Humidity, Light, Temperature
• Slow Changing phenomena
• Wide Bandwidth & Fast
Sample rate not required
• Precision Measurement is
very important
• Sensors are passive devices
• Require Biasing
• High Output Impedance
• Current Mode (Leakage)
• or Potentiometric
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Target Platform
Triad rASIC on
example array VCA-4 Digital Resources
• 24,000 ASIC Gates
• 32 Kbits of 1-Port SRAM
• 4Kx16 EEPROM, 20-Year Retention
• 48 Configurable Digital I/O
• 32KHz to 2MHz PLL
• 32 Kbits of 1-Port SRAM
• 4Kx16 EEPROM, 20-Year Retention
• 32KHz to 2MHz PLL
Analog Resources
• Low-Power, Low-Noise
• 6 Low Power Fully Differential Analog Tiles
• 8 Low Power Low Noise Single Ended Analog Tiles
• 12 Wideband/Low Noise Op-amp Tiles
• 1 Low Power Bias Generators
• 2 10-bit Digital Potentiometers
• Temperature Sensor
7. Low Cost Mixed Signal ASIC Design
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Transimpedance Amplifier (TIA)
8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Triad
Typical Quiescent Current 7.20 uA
Max Input Offset 1mV
Bandwidth 100kHz
Max Drift 5 uV/C
Input Referred Noise 300 nVrms
Min PSRR 80 dB
Min CMRR 80 dB
Triad TIA is custom designed for the application
to lower input offset and optimize bandwidth
0 50 100 150 200 250 300 350 400 450
TIA
8. Low Cost Mixed Signal ASIC Design
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Fully-Differential Amplifier (FDA)
Triad
Typical Quiescent Current 11.7 uA
Max Input Offset 1 mV
Voltage Mode Gain 1-96
Voltage Gain Steps 1.5 dB
PSRR 80 dB
CMRR 80 dB
0 50 100 150 200 250 300 350 400 450
TIA FDA
Triad FDA is custom designed for application. It
features programmable gain in steps of 1.5 dB
9. Low Cost Mixed Signal ASIC Design
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
16-bit Sigma-Delta ADC (SDADC)
Triad
ADC Reference 6.9 uA
Sigma-Delta Modulator 9.4 uA
Decimation Filter 36.9 uA
Modulator Order 2nd
Effective Number of Bits 16
Min Sample Rate 4 sps
Max Sample Rate 16 sps
Sigma Delta ADC is paired with custom digital
logic to allow direct writes to SRAM or EEPROM
without CPU intervention
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC
10. Low Cost Mixed Signal ASIC Design
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Reference System
Triad
Voltage Reference 7.9 uA
Bias Currents 37.3 uA
Buffer Amplifier 6.9 uA
Reference Noise <10 Hz 10 uVpp
Reference Noise 10 Hz -1 kHz 14 uVrms
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC References
A shared reference system has many advantages to
the distributed system inherent to discrete designs
• Less risk of noise coupling to reference system
• Reference redundancy is eliminated
• Reduces system power
• Simplified Error Budgeting
11. Low Cost Mixed Signal ASIC Design
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Buffered 8-bit DACs
Triad
8bit DAC 7.4 uA
Buffer OpAmp 3.2 uA
Triad DACs targeted at adjusting sensor Bias
voltages with low noise and high precision
Higher resolution and larger bandwidth DACs are
also supported.
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC References DACs
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Operational Amplifiers
Triad
Typical Quiescent 6.8 uA
Input Offset Voltage 1 mV
Gain Bandwidth Product 100kHz*
Noise 15 uVrms
Max Input Bias Current 100pA
PSRR 80 dB
CMRR 80 dB
Triad optimizes Gain Bandwidth Product to
minimize OpAmp Bias current
*Larger Bandwidth also available when bias
current is increased
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC References DACs OpAmps
13. Low Cost Mixed Signal ASIC Design
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Temperature Sense
Triad
Typical Quiescent 5.7 uA
Temp Range -40 to 85 deg C
Accuracy +/- 3 deg C
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC References DACs OpAmps Temp Sense
Temperature sensor is an analog
representation of die temperature which is
digitized by the on-chip ADC.
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
Clock System
Triad
Crystal Driver
71.2 uA
Low Frequency Oscillator
Frequency Range8 19.2 kHz – 1228.8 kHz
Triad’s platform includes an Low Frequency PLL
that allows a crystal referenced clock to be
dynamically adjusted to control CPU power.
For many low power microcontrollers, clocking is
limited to fixed DCO frequencies.
*Higher Frequencies supported but not required
for this application
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC References DACs OpAmps Temp Sense Clock System
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8051 CPU Core
-
+
-
+
-
+
-
+8bit DAC
8bit DAC
16bit
Sigma-Delta
ADC
TIA
TIA
-
+
-
+
Temp
Sense
Band Gap
Reference
System
EEPROM SRAM
XTAL
Driver
UART
GPIO
PLL
CPU & Peripherals
Triad
Sleep Current 2.2 uA
Active 1.29 uA/kHz
Low Power PWM Mode 35.01 uA
Active @ 38.4 kHz 71 uA
Active @ 153 kHz 181.6 uA
0 50 100 150 200 250 300 350 400 450
TIA FDA SDADC References DACs OpAmps Temp Sense Clock System Active CPU
CPU’s tailored for control of communication
interface and other AFE support functions
Triad is capable on integrating much higher
performance CPUs such as ARM Cortex-M0
16. Low Cost Mixed Signal ASIC Design
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Bringing it all together
• Assuming that the device is always on, the
Triad Solution uses 50-90% less power
• In practice, most devices utilize a power
management state machine to further
optimize power…
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Optimized Power Control State Machine
8051
CORE CLK
Voltage
Gas
Channel
1
Temp
Gas
Channel
2
ADC
ANALOG
ADC
DIGITAL
UART
RxD
Command
ResponseUART
TxD
A uA B uA C uA C uA C uA C uA E uA
D uA
tHWTOD
tRCV
tPROC
tADCPPS
tADC tDORMtXMIT
TEMP AND
VOLT SENSE
TOTAL
CURRENT
PMM
STOP
tCYCLE
Average Current 216 uA
Note: System optimizations in catalog IC designs may not be possible due to Interface, Bias and Clock system limitations
Triad’s Power Control State Machine can operate independent of CPU power state
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The Virtue of Power and Batteries
3.7V 720mAh Lithium Polymer Battery
Dimensions (mm) 30x48x5
Volume 7200 mm3
Mass 15.5 grams
Triad Solution Life ~3312 hrs = 138 days
Note: Life Calculations use extremely simple formula based on average current and capacity in mAh.
Battery parameters such as self discharge, depth of discharge, age, ESR, etc are not factored into these calculations.
3.7V 50mAh Lithium Polymer Battery
Dimensions (mm) 12x15x5
Volume 900 mm3 (87.5% less)
Mass 1.2 grams (92% less)
Triad Solution Life ~228 hrs = 9.5 days
Circuit Power Reduction Yields:
• Reduced Heat Dissipation
• Reduced Mass/Weight
• Reduced Physical Volume
• Reduced Charging Time
• Reduced Cost
Savings in Power
consumption pay dividends
across the entire system
19. Low Cost Mixed Signal ASIC Design
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220 kHz, 6.7 uA
1 MHz, 44.6 uA
11.7 MHz, 737 uA
50 MHz, 2.8 mA
300MHz, 6 mA
100
1000
10000
100000
1000000
1 10 100 1000 10000
UnityGainBandwidth(kHz)
Supply Current (uA)
IP for Every Occasion
• Using our Reconfigurable Technology we can tailor component
performance and make trade offs for your application
• These optimizations occur for every
component, Amplifiers, Filters, ADCs, Linear Regulators, Switch-Mode
Power Converters, etc.
An example
Characterization curve for
UGBW vs Supply Current
Tradeoffs
20. Low Cost Mixed Signal ASIC Design
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A Triad rASIC delivers full-custom mixed-signal performance and reduces power
consumption by 5-10x, while also reducing development costs by 70% and
development time by 50% compared to traditional full-custom approaches.
Conclusion
A Triad rASIC requires a single via mask change to reconfigure
the analog and digital functionality on the device. This via
configurable approach delivers a 5-10x reduction in power
consumption compared to designs created using catalog IC
components.
The rASIC example demonstrates a no-compromise, full-custom
analog and mixed-signal circuit performance where the designs
based on catalog IC’s are limited to the performance & cost of
products selected.
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More Information
www.TriadSemi.com
info@triadsemi.com