This document provides an introduction and overview of electronic system level (ESL) design using SystemC. It begins with background on ESL design basics, system on chip design flows, and SystemC. It then provides 3 examples of SystemC code: a counter, traffic light, and simple bus. The counter example shows a basic module with clocked process. The traffic light demonstrates a finite state machine. The bus example illustrates an interface, master/slave devices, and memory mapped components communicating over a bus. Overall, the document serves as an introductory tutorial for designing and modeling electronic systems using the SystemC language.

1. Electronic System Level(ESL)
Design and SystemC Begin
2014
NCKU CSIE
林英超蘇文鈺林敬倫

2. Outline
• Electronic System Level (ESL) Design Basics
• Hardware architecture
• SoC Design Flow (系統晶片設計流程)
• SystemC background
• SystemC Syntax by Example
– ex1: Counter
– ex2: Traffic Light
– ex3: Simple Bus

3. Why learn ESL
• if you are an undergraduate student, and/or
• if you are a C.S. student, and/or
• if you still do not know in which areas you are
really interested,
• when you still do not know what ESL is?

4. Because
• This is one of the best ways to start your
learning of C++,
• This is the best way for a C.S. student to study
SoC design,
• This is the biggest advantage C.S. students can
take over E.E. students in SoC related areas,
• This is one of the best ways to learn lots of
tools and languages in HW/SW designs.

5. What is ESL?
• ESL = Electronic System Level
• ESL doesn’t specify which levels of design should
be employed. It focuses on the concepts of
designing a system, instead of specific
components.
• Then, what is Electronic System Level design flow?
• Design, debug, verify the system using ESL
methodologies, languages, tools and CONCEPTS.

6. What does level mean?
• In HW design, level means the degree of the
design details, or the level of abstraction, of the
model of the target design. For example,
– Transistor level
– Gate level
– Register transfer level (RTL)
– Transaction level
– Behavior level
– Architecture level
– Algorithmic level
– …. And so on.

7. Before the answer is made
• Let’s ask “Why ESL design flow is needed?”
– Huge system
– Extraordinarily high complexity
– Design reuse
– Slow simulation speed
– Difficulty in integration
– Mixed/multiple disciplines
– HW/SW co-design/co-simulation/co-….
– And so on.
– Most importantly, time-to-market

8. Design Complexity from Different Design
Generation
David C. Black
Jack Donovan

9. These are not reasons
• They are just problems. Imagine
– You have a system with 10 processor cores, each
having its own memory system. There are shared
memory spaces for the cores. 20 different peripherals
to control. There are 20 programmers using 8 different
languages to develop 30 different applications on this
system which needs to support 2 different OS. And the
biggest problem is
• To cope with these problems, what do we need?

10. We need
• A super fast simulator
• A simulator supports mixed abstraction level
designs
• An integrated HW/SW co-development
environment
• A super fast simulation environment
• … and so on.
• To do this, what are the first few steps?

11. Hareware? FPGA? MCU?
• Microcontroller：
– CPU, Memory, …, etc.
– Software program
• (.C->.asm->.out)
• FPGA：
– Verlog code, VHDL code.
– Hardware program
• (.v->.bit)

12. 傳統系統(System-on-a-Board) V.S.系統晶片(System-on-a-Chip)
印刷電路板(System-on-a-Board)
CPU
IO Bridge
MPEG
Decoder
SDRAM
Disk
Video
Encoder
20 cm
系統晶片(System-on-a-Chip)
CPU
IO Bridge
MPEG
Decoder
SDRAM
Disk
Video
Encoder
2 cm

13. 傳統系統開發流程
系統規格
系統架構
硬體開發
系統雛形
軟體開發
系統整合
產品

14. 理想系統開發流程
系統規格
系統架構
硬體開發系統整合
軟體開發
產品
OPENESL : ESL design hardware
CoWare : ESL design hardware
FPGA : Hardware circuit design and verify

15. 傳統硬體開發方法
• 硬體描述語言
– VHDL, Verilog
– RTL (Register Transfer Level)
• Simulation(模擬)
– 非常慢
– Linux開機= 109小時

16. 硬體設計抽象化
Algorithm
Architecture
RTL
Gate
Transistor
Synthesis
(合成)
Abstraction
(抽象)
High Level
Low Level

17. PRODUCT DESIGN
DEVELOPMENT FLOW

18. Detailed Flow: Early stage 交互驗證
TLM/ESL Modeling stage
Final Integration Stage
Three stage pipeline design：
A. SW model: high abstraction level
model
B. TLM model：very close to
architecture
C. HW model ：HDL

19. Verification and Debugging

20. Why SystemC?
• 標準語法(IEEE Standard 1666)
– 模擬系統
– 更高抽象化
– 既有的C++開發環境
– 硬體合成
SystemC Doesn’t Speedup Simulation,
High Level does!!

21. SystemC Use Case
• 硬體工程師
– 硬體描述語言(HDL)
– 更高階、更抽象描述硬體
• 系統工程師
– System Virtual Platform (系統虛擬平台)
• Architecture Analysis (架構分析)
• Performance Exploration (效能評估)
• System Verification (系統驗證)
• 軟體工程師
– 早期開發環境
– 更多硬體資訊

22. SystemC Background
• C++
– 物件導向程式語言(Object-Oriented)
• 類別(Class)
• 純虛擬函式(pure-virtual-function)
• 硬體
– 元件(Component)
• 模組(Module)
• 介面(Interface)

23. SystemC Library
Data types
Application
Written by the end user
SystemC verification library, bus models, TLM interface
4-valued logic type
4-valued logic vectors
Bit vectors
Arbitrary-precision integers
Fixed-point types
Core Language
Module
Ports
Processes
Interfaces
Channels
Events
Methodology- and technology-specific libraies
Predefined channels
Signals, clock, FIFO,
Mutext, semaphore
Utilities
Vector, strings,
traceing
Programming Language C++

24. Module (模組)
• A Module
– A CPU
– A Gate
• With
– Port (埠口)
– Process (排程)
– Sub-module (子模組)
Top Module
Module 1 Module 1
Process Port Port Process Port Port

25. Outline
• Background
– Hardware architecture
– SoC Design Flow (系統晶片設計流程)
– SystemC background
• SystemC Syntax by Example
– ex1: Counter
– ex2: Traffic Light
– ex3: Simple Bus

26. Example 1 –
Counter (計數器)

27. #include “counter.h”
counter::process_func()
{
val = 0;
while(1)
{
wait();
val = val+1;
}
}
#include <systemc.h>
SC_MODULE(counter)
{
// port- declarstions;
sc_in_clk clk;
sc_out<int> val;
// process declarations;
void process_func();
// module constructor;
SC_CTOR(counter) {
SC_CTHREAD(process_func, clk.pos());
}
};
Module Syntax (語法)
“counter.h” “counter.cpp”

28. Run Simulation
#include “counter.h”
int sc_main(int argc, char* argv[])
{
// signal declaration
sc_clock clk(“clk”, 1, SC_NS, 0.5);
sc_signal<int> val;
// module declaration
counter counter0(“counter0”);
// signal connection
counter0.clk(clk);
counter0.val(val);
// run simulation
sc_start(100, SC_NS);
return 0;
}
“main.cpp”

29. Outline
• Background
– Hardware architecture
– SoC Design Flow (系統晶片設計流程)
– SystemC background
• SystemC Syntax by Example
– ex1: Counter
– ex2: Traffic Light
– ex3: Simple Bus

30. Example 2 –
Traffic Light (紅綠燈)

31. Finite State Mache (有限狀態機)
void fsm::cthread_func()
{
while(1) {
// red
red=true, green=false, yellow=false;
wait(10);
// green
red=false, green=true, yellow=false;
wait(10);
// yellow
red=false, green=false, yellow=true;
wait(2);
}
}

32. SC_METHOD
“light.h” “light.cpp”
#include <systemc.h>
SC_MODULE(light)
{
// port declarations
sc_in<bool> on;
// process declarations
void method_func();
// contructor
SC_CTOR(light) {
SC_METHOD(method_func);
sensitive << on;
}
};
#include “light.h”
void light::method_func()
{
if(on) {
printf(“%6lld ps: %sn”,
sc_time_stamp().value(),
name())
}
}

33. 紅綠燈
red
green
cthread on
yellow
clk
on method
on
light “red”
light “green”
method
light “yellow”
red
green
yellow method
fsm“fsm”

34. 執行結果
0 ps: red
10000 ps: green
20000 ps: yellow
22000 ps: red
32000 ps: green
42000 ps: yellow
44000 ps: red
54000 ps: green
64000 ps: yellow
66000 ps: red
76000 ps: green
86000 ps: yellow
88000 ps: red

35. Process In SystemC
• Methods
• Threads
• Clocked Threads

36. Methods
• Methods behaves like a function
• Sensitive list signals which trigger a process
can be a signal or local variable or port.

37. Threads
• Thread Process can be suspended.
• The Thread Process can contain wait() functions that
suspend process execution until an event occurs on
one of the signals the process is sensitive to.
• The process will continue to execute until the next
wait()

38. Clocked Threads
• SC_CTHREAD can have only one bit wide ports
as trigger.

39. Outline
• Background
– Hardware architecture
– SoC Design Flow (系統晶片設計流程)
– SystemC background
• SystemC Syntax by Example
– ex1: Counter
– ex2: Traffic Light
– ex3: Simple Bus

40. Example 3 –
Simple Bus (匯流排)

41. Interface
“bus_if.h:
#include <systemc.h>
class bus_if: public sc_interface {
public:
virtual void write(unsigned addr, int data) = 0;
virtual void read(unsigned addr, int& data) = 0;
};

42. Slave – RAM
#include “bus_if.h”
class ram:
public bus_if,
public sc_module {
public:
// interface function
void write(unsigned addr, int data);
void read(unsigned addr, int&data);
// constructor
ram(sc_module_name);
// destructor
~ram();
private:
// memory contents
int* pMem;
};
“ram.h”
“ram.cpp”
#include “ram.h”
ram::ram(sc_module_name nm)
: sc_module(nm)
{
pMem = new int[16];
}
ram::~ram()
{
delete[] pMem;
}
void ram::write(unsigned addr, int data)
{
pMem[addr] = data;
}
void ram::read(unsigned addr, int& data)
{
data = pMem[addr]
}

43. Slave – ROM
#include “bus_if.h”
class rom:
public bus_if,
public sc_module {
public:
// interface function
void write(unsigned addr, int data);
void read(unsigned addr, int&data);
// constructor
rom(sc_module_name);
// destructor
~rom();
private:
// memory contents
int* pMem;
};
#include “rom.h”
rom::rom(sc_module_name nm)
: sc_module(nm)
{
pMem = new int[16];
for(int i=0; i<16; i++) pMem[i] = i;
}
rom::~ram()
{
delete[] pMem;
}
void rom::write(unsigned addr, int data)
{
assert(0);
}
void rom::read(unsigned addr, int& data)
{
data = pMem[addr];
}
“rom.h”
“rom.cpp”

44. Master
#include “bus_if.h”
class cpu: public sc_module {
public:
// port declaration
sc_in_clk clk;
sc_port<bus_if> mem_port;
// process declaration
void cthread_func();
// constructor
cpu(sc_module_name nm);
};
“cpu.h”
#include “cpu.h”
cpu::cpu(sc_module_name nm)
: sc_module(nm)
{
SC_HAS_PROCESS(cpu);
SC_CTHREAD(cthread_func, clk.pos);
}
void cpu::cthread_func()
{
while(1)
{
int data;
for(int i=0; i<16; i++) {
mem_port->read(i, data);
mem_port->write(i+16, data);
}
sc_stop();
}
“cpu.cpp” }

45. Bus
cpu
bus
rom ram
master
slave
rom
ram
0x00
0x0f
0x10
0x1f
Memory
Map

46. Bus
#include “bus_if.h”
class bus:
public bus_if,
public sc_module {
public:
// port declaration
sc_port<bus_if> rom_port;
sc_port<bus_if> ram_port;
// interface function
void write(unsigned addr, int data);
void read(unsigned addr, int&data);
// constructor
bus(sc_module_name);
};
#include “bus.h”
bus::bus(sc_module_name nm)
: sc_module(nm)
{
}
void bus::write(unsigned addr, int data)
{
if(addr < 16)
rom_port->write(addr, data);
else
rqm_port->write(addr, data);
}
void bus::read(unsigned addr, int& data)
{
if(addr < 16)
rom_port->read(addr, data);
else
ram_port->read(addr, data);
}
“bus.h”
“bus.cpp”

47. • www.doulos.com/knowhow/systemc/
• www.asic-world.com/systemc/
• www.systemc.org/

48. TOOLS

49. Commercial tool: SOC Designer
Work Space
Cache Profiling window
Waveform Viewer
Memory maps
Assembly code window

50. Commercial tool: CoWare

51. Open Source: GreenSoc (not so open)
User IP 1 GreenBus I/F
GreenScript
SystemC
User IP 2
User IP 3
Config User I/F
GreenBus I/F
GreenBus I/F
Config User I/F
Config User I/F
Config PlugIn
GreenAV PlugIn
Specific PlugIn
GreenControl Core
GreenAV User I/F
Specific User I/F
ESL
Tools

52. SCREAM Lab OpenESL

53. SCREAM Lab OpenESL

54. FPGA tool:
Berkeley BEE2

55. FPGA tool: NCKU Multicore

56. FPGA tool: SMIMS

57. LAB 1
SystemC 環境建構及範例程式運行

58. 安裝說明
• 請參閱doc檔。
• 環境統一使用Linux。

59. 專案說明
• 其中包含三個檔案main.cpp hello_module.h
hello_module.cpp
• 可將main.cpp視同電路板，在上面做接線等
等的動作。
• hello_module是一個具有process的硬體元件。

60. Main.cpp
將所需元件的.h檔和systemC.h引入
Sc_main是systemC程式的進入點
宣告一組clk的訊號週期為10ns
宣告一組hello_module的元件
將clk接上module的clk訊號上
開始進行模擬模擬1000ns內的硬體
運作

61. Hello_module.h
宣告一組元件定義hello_module
宣告hello_module的訊號線clk
宣告hello_module的運作函式
hello_module的建構子
整組元件具有process(method)
process執行的函式Method_func
Process會經由clk正緣觸發

62. Hello_module.cpp
運作函式本體
訊號有產生改變才執行
印出模擬時間
印出hello word!

63. 執行結果