This document discusses the potential for higher performance solid state drives (SSDs) using a new interface standard called HyperLink NAND (HLNAND). HLNAND uses a daisy-chained ring connection that allows for higher speeds and scalability compared to parallel bus interfaces. An HLNAND SSD prototype demonstrated single channel read and write speeds of up to 213MB/s and 130MB/s respectively. Next generation HLNAND2 technology is expected to provide up to 800MB/s per channel, enabling multi-channel SSDs to reach over 1GB/s throughput. HLNAND simplifies SSD design and lowers costs by reducing the need for complex protocol conversion and fewer channels to achieve high performance.

1. Looking Ahead to Higher
Performance SSDs with HLNAND
(A New Standard for GB/s-Class SSDs)
Roland Schuetz
Director, Applications & Business Initiatives
MOSAID Technologies Inc.
Soogil Jeong
Vice President, Engineering
INDILINX
Flash Memory Summit 2010
Santa Clara, CA

2. High-Speed Infrastructure in Place
Data Rate (Gbps)
PCIe 3.0 (8Gbps/Lane)
6 SATA-III (6Gbps)
5 PCIe 2.0 (5Gbps/Lane)
USB3.0 (4.8Gbps)
4
FireWire3200 (3.2Gbps)
3 SATA-II (3Gbps)
PCIe 1.1 (2.5Gbps/Lane)
2
SATA-I (1.5Gbps)
1
FireWire800 (800Mbps)
FireWire400 (400Mbps)
USB2.0 (480Mbps)
1995 USB1.0 (12Mbps) 2000 2005 2010 Year
Flash Memory Summit 2010
Santa Clara, CA

3. HLNAND in a Nutshell
HyperLink interface: Daisy-chain ring, point-to-point
connections
Cleaner signalling than parallel bus
Higher speed & no roll-off with increasing loads
SCALABILITY

4. HLNAND SSD Prototype
Flash Memory Summit 2010
Santa Clara, CA

5. HLNAND SSD Flash Anatomy
40MB/s
128GB on a single channel 40MB/s
of HLNAND MCPs 40MB/s
40MB/s
133MHz, DDR266
HyperLink interface 64Gb HLNAND
16 MCP, 64 independent
banks 64GB HLDIMM
Data addressable 512B –
4KB virtual page size
Flash Memory Summit 2010
Santa Clara, CA

6. HLNAND SSD System Anatomy
APB ROM
ARM7
Bridge SRAM
SDRAM FPGA AHB Sync
64MB Bridge
Host I/F SATA PHY SDRAM Control Buffer HLNAND
(SATA2) Chip Arbiter Control Control
HLNAND HLNAND HLNAND HLNAND HLNAND HLNAND HLNAND HLNAND
64Gb 64Gb 64Gb 64Gb 64Gb 64Gb 64Gb 64Gb
HLNAND HLNAND HLNAND HLNAND HLNAND HLNAND HLNAND HLNAND
64Gb 64Gb 64Gb 64Gb 64Gb 64Gb 64Gb 64Gb
HLDIMM_1 64GB HLDIMM_0 64GB
Flash Memory Summit 2010
Santa Clara, CA

7. HLNAND SSD Per-Channel
Performance Single Channel Performance
@ 75MHz (FPGA limit)
• 120MB/s/ch. seq. read
• 73MB/s/ch. seq. write
@ 133MHz, translates to:
• 213MB/s/ch. seq. read
• 130MB/s/ch. seq. write
8 Ch. HL SSD capable of 1.7GB/s
read, 1.0GB/s write
GB/s-Class SSDs now possible
with HLNAND
Flash Memory Summit 2010
Santa Clara, CA

8. Introducing HLNAND2
Source synchronous clocking
JEDEC HSUL_12 interface up to DDR800
Independent automatic status bus
Flash Memory Summit 2010
Santa Clara, CA

9. HLNAND2 Features
DDR533 / DDR667 / DDR800
JEDEC 1.2V HSUL_12 Interface Signaling
Source Synchronous Clock CK & CK#
Four bank architecture
Fully independent 8 die operation
Built-in EDC (Error Detection Code)
DuplexRW™: Simultaneous DDR800 read &
write, effectively 1600MB/s data throughput
Independent automatic status bus
Flash Memory Summit 2010
Santa Clara, CA

10. 256Gb MLC HLNAND2 MCP
100-Balls BGA (18mm x 14mm)
Flash Memory Summit 2010
Santa Clara, CA

11. Throughput Advantage of HLNAND
Within tR
Flash Pg. Size & Read Time

12. High-Speed NAND Comparisons
Toggle-
HLNAND2 HLNAND ONFi 2.0
Mode
Synchro
nous IO Yes Yes Yes No
Transfer
rate 800MT/s 266MT/s 166MT/s 133MT/s
Clock 67MHz
speed 400 MHz 133MHz 83MHz
(DQS)
# die
before 255 255 8 8
roll-off
Flash Memory Summit 2010
Santa Clara, CA

13. Current High-Speed Enterprise
SSD Architecture
• Multi-stage fan-out from high-speed 240 Mbps–
serial channel to low speed parallel channel 1.2Gbps
• Requires several stages of intermediate SATA2 Flash
protocol conversion Flash
• Several types of hardware Ctlr Flash
3Gbps
and firmware support
SATA2 Flash
Flash
PCIe to Ctlr Flash
Host SATA2
Bridge
SATA2 Flash
Flash
Ctlr Flash
Flash Memory Summit 2010
Santa Clara, CA

14. Simplification with HLNAND
Up to 6.4Gbps
HL HL
Up to 12.8Gbps
(PCIe v2.x, x32)
HL HL
PCIe /
Host HLNAND
controller
HL HL
HL HL
• Fewer stages of protocol translation and fewer different devices
• Can implement host interface, controller, and flash interface in
single ASIC
• Fewer channels to achieve maximum throughput; therefore lower
ECC, IO, and PCB costs
• 8 ch. SSD with DDR800 HLNAND2 achieves 6.4GB/s data rate
Flash Memory Summit 2010
Santa Clara, CA

15. Summary
Adoption of faster interfaces is progressing
HLNAND2 provides 800MB/s/ch. transfer rate
HLNAND2 throughput matched closely with
high-speed system interconnect like PCIe 2.x &
PCIe 3.0
System design simplified with HLNAND
Higher system throughput with less complexity
Controller cost reduced through duplication
reduction (ECC logic, IO)
Higher scalability in performance & capacity
Flash Memory Summit 2010
Santa Clara, CA

16. Resource for HLNAND Flash
www.HLNAND.com
Flash Memory Summit 2010
Santa Clara, CA