SlideShare a Scribd company logo

Clock Skew 1

•
•
R
rchovatiya

This PPT for Clock Skew Solution Method.

1 of 10
Clock Skew
Clock Skew ,[object Object],[object Object],[object Object]
Clock Skew ,[object Object],[object Object],The buffering method of figure (a) produces excessive clock skew, since CLOCK1 and CLOCK2 are delayed through an extra buffer compared to CLOCK. A recommended method is shown in figure (b). All of the clock signals go through identical buffers, and thus have roughly equal delays.
Minimizing the clock skew ,[object Object],The amount of the inserted delay (number of BUFD or INVD macros) in the data path should be large enough so that the delay becomes sufficiently greater than the clock skew.
Minimizing the clock skew ,[object Object],In this method, the clock signal arrives at the clock port of the destination register sooner than the source register. Therefore, the destination register will clock in the source register (current) value before the source register receives it’s clock edge. The clock reversing method will not be effective in circular structures such as Johnson counters because it is not possible to define the source register explicitly.
Minimizing the clock skew ,[object Object],In this example, the clock skew problem exists between flip-flops U1 and U3.
Minimizing the clock skew ,[object Object],[object Object],[object Object],[object Object],[object Object],In this method, the sequentially adjacent registers are clocked on opposite edges of the clock. This method provides a short path-clock skew margin of about one-half clock cycle.
Minimizing the clock skew ,[object Object]
Minimizing the clock skew ,[object Object],In this method, the sequentially adjacent registers are alternatively clocked on two different phases of the same clock. In this case, between each two adjacent registers, there is a safety margin approximately equal to the phase difference of the two phases.
[object Object]

Recommended

Clock Skew 2
Clock Skew 2Clock Skew 2
Clock Skew 2rchovatiya
 
VLSI Power Reduction
VLSI Power ReductionVLSI Power Reduction
VLSI Power ReductionMahesh Dananjaya
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedyUsha Mehta
 
ATPG Methods and Algorithms
ATPG Methods and AlgorithmsATPG Methods and Algorithms
ATPG Methods and AlgorithmsDeiptii Das
 
VLSI routing
VLSI routingVLSI routing
VLSI routingNaveen Kumar
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design pptAnil Yadav
 
FPGA
FPGAFPGA
FPGAsubin mathew
 
Vlsi testing
Vlsi testingVlsi testing
Vlsi testingDilip Mathuria
 

Recommended

Clock Skew 2
Clock Skew 2Clock Skew 2
Clock Skew 2rchovatiya
 
VLSI Power Reduction
VLSI Power ReductionVLSI Power Reduction
VLSI Power ReductionMahesh Dananjaya
 
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedy13 static timing_analysis_4_set_up_and_hold_time_violation_remedy
13 static timing_analysis_4_set_up_and_hold_time_violation_remedyUsha Mehta
 
ATPG Methods and Algorithms
ATPG Methods and AlgorithmsATPG Methods and Algorithms
ATPG Methods and AlgorithmsDeiptii Das
 
VLSI routing
VLSI routingVLSI routing
VLSI routingNaveen Kumar
 
Low power vlsi design ppt
Low power vlsi design pptLow power vlsi design ppt
Low power vlsi design pptAnil Yadav
 
FPGA
FPGAFPGA
FPGAsubin mathew
 
Vlsi testing
Vlsi testingVlsi testing
Vlsi testingDilip Mathuria
 
SOC Processors Used in SOC
SOC Processors Used in SOCSOC Processors Used in SOC
SOC Processors Used in SOCA B Shinde
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Usha Mehta
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehtaUsha Mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designUsha Mehta
 
Power Gating
Power GatingPower Gating
Power GatingMahesh Dananjaya
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossingUsha Mehta
 
Design for Testability
Design for Testability Design for Testability
Design for Testability kumar gavanurmath
 
Design for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDesign for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDilip Mathuria
 
Scan insertion
Scan insertionScan insertion
Scan insertionkumar gavanurmath
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfUsha Mehta
 
Latch up
Latch upLatch up
Latch upishan111
 
System on chip architectures
System on chip architecturesSystem on chip architectures
System on chip architecturesA B Shinde
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flowRajendra Kumar
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)shaik sharief
 
fpga programming
fpga programmingfpga programming
fpga programmingAnish Gupta
 
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Usha Mehta
 
CMOS TG
CMOS TGCMOS TG
CMOS TGaghila1994
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySudhanshu Janwadkar
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 
Cpld fpga
Cpld fpgaCpld fpga
Cpld fpgaanishgoel
 
Clock distribution in high speed board
Clock distribution in high speed boardClock distribution in high speed board
Clock distribution in high speed boardPankaj Khodifad
 
Types of cro
Types of croTypes of cro
Types of croAnilAgarwal84
 

More Related Content

What's hot

SOC Processors Used in SOC
SOC Processors Used in SOCSOC Processors Used in SOC
SOC Processors Used in SOCA B Shinde
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Usha Mehta
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehtaUsha Mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designUsha Mehta
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossingUsha Mehta
 
Design for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDesign for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDilip Mathuria
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfUsha Mehta
 
System on chip architectures
System on chip architecturesSystem on chip architectures
System on chip architecturesA B Shinde
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)shaik sharief
 
fpga programming
fpga programmingfpga programming
fpga programmingAnish Gupta
 
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Usha Mehta
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySudhanshu Janwadkar
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing TechniquesA B Shinde
 

What's hot (20)

SOC Processors Used in SOC
SOC Processors Used in SOCSOC Processors Used in SOC
SOC Processors Used in SOC
 
Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)Design-for-Test (Testing of VLSI Design)
Design-for-Test (Testing of VLSI Design)
 
Sta by usha_mehta
Sta by usha_mehtaSta by usha_mehta
Sta by usha_mehta
 
Introduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi designIntroduction of testing and verification of vlsi design
Introduction of testing and verification of vlsi design
 
Power Gating
Power GatingPower Gating
Power Gating
 
14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing14 static timing_analysis_5_clock_domain_crossing
14 static timing_analysis_5_clock_domain_crossing
 
Design for Testability
Design for Testability Design for Testability
Design for Testability
 
Design for testability and automatic test pattern generation
Design for testability and automatic test pattern generationDesign for testability and automatic test pattern generation
Design for testability and automatic test pattern generation
 
Scan insertion
Scan insertionScan insertion
Scan insertion
 
Static_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdfStatic_Timing_Analysis_in_detail.pdf
Static_Timing_Analysis_in_detail.pdf
 
Latch up
Latch upLatch up
Latch up
 
System on chip architectures
System on chip architecturesSystem on chip architectures
System on chip architectures
 
Vlsi design flow
Vlsi design flowVlsi design flow
Vlsi design flow
 
Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)Multi mode multi corner (mmmc)
Multi mode multi corner (mmmc)
 
fpga programming
fpga programmingfpga programming
fpga programming
 
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
Deterministic Test Pattern Generation ( D-Algorithm of ATPG) (Testing of VLSI...
 
CMOS TG
CMOS TGCMOS TG
CMOS TG
 
Silicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) TechnologySilicon on Insulator (SOI) Technology
Silicon on Insulator (SOI) Technology
 
VLSI Testing Techniques
VLSI Testing TechniquesVLSI Testing Techniques
VLSI Testing Techniques
 
Cpld fpga
Cpld fpgaCpld fpga
Cpld fpga
 

Similar to Clock Skew 1

Clock distribution in high speed board
Clock distribution in high speed boardClock distribution in high speed board
Clock distribution in high speed boardPankaj Khodifad
 
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPDESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPVLSICS Design
 
A 20 gbs injection locked clock and data recovery circuit
A 20 gbs injection locked clock and data recovery circuitA 20 gbs injection locked clock and data recovery circuit
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
 
Timing issues in digital circuits
Timing issues in digital circuitsTiming issues in digital circuits
Timing issues in digital circuitsaroosa khan
 
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUITA 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUITVLSICS Design
 
EEL316: Pseudo Random Bit Generation
EEL316: Pseudo Random Bit GenerationEEL316: Pseudo Random Bit Generation
EEL316: Pseudo Random Bit GenerationUmang Gupta
 
Design of -- Two phase non overlapping low frequency clock generator using Ca...
Design of -- Two phase non overlapping low frequency clock generator using Ca...Design of -- Two phase non overlapping low frequency clock generator using Ca...
Design of -- Two phase non overlapping low frequency clock generator using Ca...Prashantkumar R
 
Jack_Knutson_SNUG2003_ Copy
Jack_Knutson_SNUG2003_ CopyJack_Knutson_SNUG2003_ Copy
Jack_Knutson_SNUG2003_ CopyJack Knutson
 
Timing notes 2006
Timing notes 2006Timing notes 2006
Timing notes 2006pavan kumar
 
Library Characterization Flow
Library Characterization FlowLibrary Characterization Flow
Library Characterization FlowSatish Grandhi
 
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...eSAT Publishing House
 
Scan-Based Delay Measurement Technique Using Signature Registers
Scan-Based Delay Measurement Technique Using Signature RegistersScan-Based Delay Measurement Technique Using Signature Registers
Scan-Based Delay Measurement Technique Using Signature RegistersIJMER
 
Vlsi lab viva question with answers
Vlsi lab viva question with answersVlsi lab viva question with answers
Vlsi lab viva question with answersAyesha Ambreen
 
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...IJTET Journal
 

Similar to Clock Skew 1 (20)

Clock distribution in high speed board
Clock distribution in high speed boardClock distribution in high speed board
Clock distribution in high speed board
 
Types of cro
Types of croTypes of cro
Types of cro
 
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOPDESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP
DESIGN AND IMPLEMENTATION OF AREA AND POWER OPTIMISED NOVEL SCANFLOP
 
A 20 gbs injection locked clock and data recovery circuit
A 20 gbs injection locked clock and data recovery circuitA 20 gbs injection locked clock and data recovery circuit
A 20 gbs injection locked clock and data recovery circuit
 
Sta
StaSta
Sta
 
Timing issues in digital circuits
Timing issues in digital circuitsTiming issues in digital circuits
Timing issues in digital circuits
 
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUITA 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT
A 20 Gb/s INJECTION-LOCKED CLOCK AND DATA RECOVERY CIRCUIT
 
EEL316: Pseudo Random Bit Generation
EEL316: Pseudo Random Bit GenerationEEL316: Pseudo Random Bit Generation
EEL316: Pseudo Random Bit Generation
 
Design of -- Two phase non overlapping low frequency clock generator using Ca...
Design of -- Two phase non overlapping low frequency clock generator using Ca...Design of -- Two phase non overlapping low frequency clock generator using Ca...
Design of -- Two phase non overlapping low frequency clock generator using Ca...
 
Unit 4 ei
Unit 4 eiUnit 4 ei
Unit 4 ei
 
Jack_Knutson_SNUG2003_ Copy
Jack_Knutson_SNUG2003_ CopyJack_Knutson_SNUG2003_ Copy
Jack_Knutson_SNUG2003_ Copy
 
Clock Distribution
Clock DistributionClock Distribution
Clock Distribution
 
CRO
CROCRO
CRO
 
Timing notes 2006
Timing notes 2006Timing notes 2006
Timing notes 2006
 
Library Characterization Flow
Library Characterization FlowLibrary Characterization Flow
Library Characterization Flow
 
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...
Design and implementation of synchronous 4 bit up counter using 180 nm cmos p...
 
A02100104
A02100104A02100104
A02100104
 
Scan-Based Delay Measurement Technique Using Signature Registers
Scan-Based Delay Measurement Technique Using Signature RegistersScan-Based Delay Measurement Technique Using Signature Registers
Scan-Based Delay Measurement Technique Using Signature Registers
 
Vlsi lab viva question with answers
Vlsi lab viva question with answersVlsi lab viva question with answers
Vlsi lab viva question with answers
 
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
Design of an ADC using High Precision Comparator with Time Domain Offset Canc...
 

Clock Skew 1