Theertharamesh L C
29
Seguidores
Personal Information
Organização/Local de trabalho
Bengaluru Area, India India
Cargo
FPGA& RTL DESIGN ENGINEER at MINDFLOW
Setor
Electronics / Computer Hardware
Sobre
Overall experience of 2.8 years in RTL Design & FPGA board design
Experience in RTL design, Microarchitecture, On-chip debugging.
Experience in writing Verilog testbench for simulating RTL design before implementing on
FPGAs
Good working knowledge on Xilinx FPGA and development tools
•Good Experience SOC and ARM Architecture
•Excellent understanding of Protocols such as AMBA AXI4 .
• good knowledge of Modelsim, Questasim tools. Familiar with Object Oriented Programming.
Area of Interest:
Digital System Design,
VLSI Design,
Embedded System Design.
IP design & verification
SKILL SET
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HDL’s : Verilog
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EDA Tools : QuestaSim (Mentor...
- Apresentações
- Documentos
- Infográficos
Verilog HDL
Mantra VLSI
•
Há 11 anos
Sequential Circuits - Flip Flops (Part 2)
Abhilash Nair
•
Há 11 anos
Verilog 語法教學
艾鍗科技
•
Há 11 anos
UAV Presentation
Ruyyan
•
Há 15 anos
SOC Verification using SystemVerilog
Ramdas Mozhikunnath
•
Há 10 anos
Spi master core verification
Maulik Suthar
•
Há 11 anos
IP Reuse Impact on Design Verification Management Across the Enterprise
DVClub
•
Há 11 anos
Uvm dcon2013
sean chen
•
Há 10 anos