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resume_parbhat

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  1. 1. Parbhat Kangra 153070081 Electrical Engineering M.Tech. IIT Bombay Male Specialization: Electronic Systems DOB: 26 Sep 1992 Examination University Institute Year CPI / % Post Graduation IIT Bombay IIT Bombay 2017 8.21 Undergraduate Specialization: Electronics & Communication Graduation NIT Kurukshetra NIT Kurukshetra 2014 7.37 Intermediate/+2 CBSE Shiksha Bharti Vidyalay 2010 75.20 Matriculation CBSE Shiksha Bharti Vidyalay 2008 67.80 AREAS OF INTEREST Digital VLSI Design, Testing and Verification, Analog VLSI Design, Embedded Systems TECHNICAL SKILLS • Tools: NGSpice, Modelsim, Xilinx, Noxim Simulator, GHDL, MATLAB, EAGLE, Code Composer Studio • Languages: VHDL, Verilog, System C (HDL), C, C++, Python (Programming)) MAJOR PROJECTS • M.Tech Project (Ongoing) (May 2016 - Present) Title: Fault Tolerant Routing for Network on Chip(NoC) Architecture Guide: Prof. Virendra Singh, IIT Bombay Keywords: NoC, Packet, Deadlock, Livelock Idea: Development of a new fault tolerant routing algorithm for NoC architecture o Routing Algorithm should cover any number of link failures in the network o This research work focuses on error free transmission of packets in the network Ongoing and Future Work: o Studied several design approach for reliable data delivery under faulty environment o Deadlock and Livelock avoidance is to provided in the network o Intra-router soft error is to be studied and dedicated hardware can be used o Link-Level Fault Detection and Protection can be provided using hamming codes • M.Tech Seminar (January - May 2016) Title: Design Methodology and Research Approach for NoCs Guide: Prof. Virendra Singh, IIT Bombay o Studied several research challenges, and motivation for the design and corresponding approach o Analysed different design constraints which should be considered during designing of NoC o Timing-error-tolerant design methodology, parity routing, and packet chaining concepts were studied • B.Tech Project (January - May 2014) Title: Implementation of IEEE 754 Standard (FPU) on FPGA Guide: Prof. Mohammad Arif, NIT Kurukshetra o Implementation of 8-bit FPU on SPARTAN 3E FPGA using VHDL o Arithmetic, logical, and shift, all 16 operations were implemented RELEVANT COURSES • VLSI Design • Testing and Verification of VLSI circuits • VLSI Design Lab • CMOS Analog VLSI Design • System Design • DSP Application • Electronic System Design • DSP Implementation • Foundation of VLSI CAD • Embedded System Design COURSE PROJECTS • Automatic Test Pattern Generator (ATPG) (Course: Testing and Verification) o Implemented PODEM algorithm in C++ for combinational circuits o Simulated for c17 benchmark and few other circuits written in Verilog 1
  2. 2. • Design of Lift Group Control System (LGCS) (Course: VLSI Design Lab) o Implemented in VHDL and Verilog, an elevator controller for 3 lifts in a 6 floor building o Designed the controller for minimizing average waiting time of passengers • Design of Router for NoC (Course: VLSI Design Lab) o Implemented in Verilog and System C, a router that uses Distance Ordered Routing o Synthesized the design and performed post synthesis simulation • Design of Run Length Encoder (Course: VLSI Design Lab) o A data compression circuit was implemented in Verilog using run length encoding o It replaces repeated occurrences of a byte by the repeat count and the byte value • Design of Greatest Common Divisor (Course: VLSI Design Lab) o GCD of the two numbers was found using Stein’s algorithm with proper handshake signals o Stein’s algorithm replaces division with arithmetic shifts, comparisons, and subtraction o GCD result was verified using distinct set of numbers • Design of Dadda and Wallace Multipliers (Course: VLSI Design) o Implemented in VHDL for signed multiplication of two 8-bit numbers o Carry select architecture for the final adder with square root stacking was used • Design of folded cascode OpAmp with CMFB (Course: CMOS Analog VLSI Design) o Designed a two stage folded cascode opamp in 180 nm CMOS technology in Ngspice o Specification was 90 dB gain, 67 MHz UGB, 66◦ PM for a load capacitor of 10 pF and input common mode range of 0.6 V for a supply voltage of 1.8V considering differential slew rate better than 20 V/uS • Digital Tuner for Guitar (Course: DSP Implementation) o Implemented in real time using Texas Instruments TMS320C5515 DSP processor board o Silence Region Detection, FFT, Autocorrelation, and Peak Detection Blocks were used TECHNICAL WORKSHOPS • Industrial training on electronic relays at C&S Electric Limited, New Delhi (May - July 2013) • Summer Training in Embedded Robotics at HP Educational Centre, Noida (June - July 2012) • Workshops on robotics organized by EFY and Emanagineer at NIT Kurukshetra POSITIONS OF RESPONSIBILITY • Coordinator in Mood Indigo (December 2015) o Organised 3 events as a coordinator of INFORMALS team, o Sniffer Squad, Minute to win it, Segway racing • Teaching Assistant o Introduction to Electronics(EE112): Worked out few assignments and did invigilation duty o VLSI Design(EE671): Responsible for evaluating assignments and answer scripts EXTRA CURRICULAR • 1st Prize in Battle of Bands competition at NIT Kurukshetra (February 2011) • 2nd Prize in Instrumental solo competition at NIT Kurukshetra (February 2013) • Participated in a Band Competition in PGCult at IIT Bombay (February 2016) OTHER INTERESTS • Appreciating Music, Playing Musical Instruments, Making Dubsmash, Martial Arts, Meditation, & Reiki 2

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