Chapter 5: Combinational Logic with MSI and LSI

1. Er. Nawaraj Bhandari
Digital Logic
Chapter 5:
Combinational Logic with MSI and
LSI

2. INTRODUCTION
 The purpose of Boolean-algebra simplification is to
obtain an algebraic expression that, when implemented,
results in a low-cost circuit.
 Two circuits that perform the same function, the one that
requires fewer gates is preferable because it will cost
less.
 But this is not necessarily true when integrated circuits
are used. With integrated circuits, it is not the count of
gates that determines the cost, but the number and types
of ICs employed and the number of interconnections
needed to implement the digital circuits of varying
complexities (I mean circuits with different level of
integrations viz. SSI, MSI, LSI, VLSI, ULSI etc).

3.  MSI components perform specific digital functions commonly needed in the
design of digital systems.
 Combinational circuit-type MSI components that are readily available in IC
packages are
 binary adders
 subtractors
 comparators,
 decoders,
 encoders, and
 multiplexers.
 These components are also used as standard modules within more complex LSI
and VLSI circuits and hence used extensively as basic building blocks in the
design of digital computers and systems.

4. ADDERS
 This circuit sums up two binary numbers A and B of n-bits
using full-adders to add each bit-pair & carry from
previous bit position.
 The sum of A and B can be generated in two ways:
either in a serial fashion or in parallel.
 1. 4-bit parallel binary adder
 2. Binary Parallel adder
 3. Decimal Adder – BCD adder


5. 4-Bit parallel adder using full adder
 This circuit sums up two binary numbers A and B of n-bits
using full-adders to add each bit-pair & carry from
previous bit position.
 The outputs carry from one full-adder is connected to the
input carry of the full-adder one position to its left.
 As soon as the carries are generated, the correct sum
bits emerge from the sum outputs of all full-adders.
 Let’s assume A=A3 A2 A1 A0
 B=B3 B2 B1 B0 AND INITIALY
carry is Cin =0

6. Bcd Adder
 Computers or calculators that perform arithmetic operations
directly in the decimal number system represent decimal
numbers in binary-coded form
 Where decimal is 0-9
 And bcd also 0-9, greater than 9 is don’t care
 In the bcd adder it sis cmbination of two 4bit adder.
 And output will be 18 0r 19 bit
 Let assume A=0-3,B=0-3
 Binary code-0000 to 1001 from both side
 Total=9+9+1=19
 Or 9+9=18 without adding carry.

7.  Also Known as 8421 digit.
 A 4-bit binary adder.
 Adds two 4-bit digits having a BCD.
 Resulting format 4-bit output digit.
 Sum exceeding decimal value of 9, a carry’s generated.
What is BCD ADDER?

8. Conversion and Coding
(12)10
1100 00010010Conversion
Coding
(using BCD code
for each digit)

9. FUNCTIONS OF BCD ADDER
 A 4-bit BCD code’s used to represent 0 to 9 digits.
 Adding BCD numbers using BCD addition.
 Adding 6 with the sum while exceeding 9 and generating a carry.
 By adding 6 to the sum, make an invalid digit valid.

10. Addition with bcd adder
Maximum sum is 9+9 + 1 = 19
Max digit Carry from previous digits

11. Bcd adder (sum up to 9)
Number C S3 S2 S1 S0
0 0 0 0 0 0
1 0 0 0 0 1
2 0 0 0 1 0
3 0 0 0 1 1
4 0 0 1 0 0
5 0 0 1 0 1
6 0 0 1 1 0
7 0 0 1 1 1
8 0 1 0 0 0
9 0 1 0 0 1

12. Bcd adder (sum is 10 to 19)
Number C S3 S2 S1 S0
10 1 0 0 0 0
11 1 0 0 0 1
12 1 0 0 1 0
13 1 0 0 1 1
14 1 0 1 0 0
15 1 0 1 0 1
16 1 0 1 1 0
17 1 0 1 1 1
18 1 1 0 0 0
19 1 1 0 0 1

13. Bcd adder (sum is 10 to 19)
BCD adder sum Binary sum
Number
C S3 S2 S1 S0
10 1 0 0 0 0
11 1 0 0 0 1
12 1 0 0 1 0
13 1 0 0 1 1
14 1 0 1 0 0
15 1 0 1 0 1
16 1 0 1 1 0
17 1 0 1 1 1
18 1 1 0 0 0
19 1 1 0 0 1
K s3 s2 s1 s0
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 0 1
1 0 0 1 0
1 0 0 1 1
+6

14. Algorithm for bcd adder
 If sum is up to 9
Use the regular Adder.
 If the sum > 9
Use the regular adder and add 6 to the result

15. Why add 6 to the result?
 Sum of two BCD digits exceeding 9.
 A carry is generated.
 Converting the invalid digit into valid digit.
 Carry generated by adding 6 to the invalid BCD digit’s
passed on to the next BCD digit.

16. When is the result>9
Binary sum
Number
K S3 S2 S1 S0
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
C = K +

17. When is the result>9
Binary sum
Number
K S3 S2 S1 S0
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
C = K + S3*S2+

18. When is the result>9
Binary sum
Number
K S3 S2 S1 S0
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
C = K + S3*S2+
S3*S1

19. 4-bit bcd adder
4-bit Adder
4-bit Adder
0 0
s3 s2 s1 s0
S3 S2 S1 S0
Cin
K
0 1 1 00 1 1
1
1 1 0 1
0
1 1 0 1
1 1
1
0 0 1 1
1
0
1

20. Magnitude Comparator
 A digital comparator or magnitude comparator is a
hardware electronic device that takes two numbers as
input in binary form and determines whether one number
is greater than,
 less than or
 equal to the other number.
 Comparators are used in central processing unit s
(CPUs) and microcontrollers (MCUs).
 Magnitude Comparator – a Magnitude Comparator is a
digital comparator which has three output terminals, one
each for equality,
 A = B greater than, A > B and less than A < B

21.  1-bit Digital Comparator Circuit
Inputs Outputs
B A
A >
B
A = B
A <
B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0

22.  4-bit Magnitude Comparator
Some commercially available digital comparators such as
the
TTL 74LS85 or
CMOS 4063
4-bit magnitude comparator have additional input
terminals that allow more individual comparators to be
“cascaded” together to compare words larger than 4-bits
with magnitude comparators of “n”-bits being produced

23.  A = A3A2A1A0
 B = B3B2B1B0
 if A3 = B3 and A2 = B2 and A1 = B1 and A0 = B0
 Xi = AiBi + Ai’Bi’, i = 0, 1, 2, 3
 Algorithm
 (A = B)
 For the equality condition to exist, all Xi variables must be
equal to 1. This dictates an AND operation of all variables:
 (A = B) = X3X2X1X0
 A > B: If the corresponding digit of A is 1 and that of B is 0.
 A < B: If the corresponding digit of A is 0 and that of B is 1.

24.  (A > B) = A3B3’ + X3A2B2’ + x3x2A1B1’ + X3X2X1A0B0’
 (A < B) = A3’B3 + X3A2’B2 + x3x2A1’B1 + X3X2X1A0’B0

25. Encoder
 Encoder, decoder and multiplexer is the part of MSI
 Encoder have n input and m outputs
 Function of decoder is opposite to the encoder
 Encoder can encode code in minimum no.of dataline and decoder decode it.
 If we have 4*2 encoder it means 2*4 decoder is used.
 So relation between encoder and decoder is:
 N=2M
 in 4*2, 8*3,16*4 encoder the input will be 4,8,16 resp. and output will be 2,3,4
dataline.
 Decoder is a combinational circuit that converts binary information from n
input lines to a maximum of 2n unique output lines.
 If the n-bit decoded information has unused or don't-care combinations, the
decoder output will have fewer than 2n outputs.

26.  Priority encoders
 Decimal to BCD encoder
 Octal to binary encoder
 Hexadecimal to binary encoder
 Priority encoders:-This is a special type of encoder. Priority
is given to the input lines. If two or more input line are 1 at
the same time, then the input line with highest priority will be
considered. There are four input D0, D1, D2, D3 and two
output Y0, Y1. Out of the four input D3 has the highest
priority and D0 has the lowest priority. That means if D3 = 1
then Y1 Y1 = 11 irrespective of the other inputs. Similarly if
D3 = 0 and D2 = 1 then Y1 Y0 = 10 irrespective of the other
inputs.

27. Octal to Binary encoder
 An encoder is a digital function that produces a reverse
operation from that of a decoder.
 An encoder has 2n (or less) input lines and n output lines.
The output lines generate the binary code for the 2n input
variables.
 The octal-to-binary encoder consists of eight inputs, one for
each of the eight digits,
 and three outputs that generate the corresponding binary
number.
 It is constructed with OR gate whose inputs can be determined
from the truth table.
 Let A=4+5+6+7
 B=2+3+6+7
 C=1+2+5+7

28. Decoder
 A decoder is a combinational circuit. It has n input and to a
maximum m = 2n outputs. Decoder is identical to a
demultiplexer without any data input.
 It performs operations which are exactly opposite to those
of an encoder.
 A decoder can take minimum input and generate maximum
output of its combination.
 N=2n where N is no. of inputs and 2n is output.


29. Combinational logic
Implementation
 A decoder provides the 2n minterm of n input variables.
 Boolean function can be expressed in sum of minterms
canonical form, one can use a decoder to generate the
minterms and an external OR gate to form the sum.
 Any combinational circuit with n inputs and m outputs
can be implemented with an n-to-2n- line decoder and m
OR gates.
 Example: Implement a full-adder circuit with a decoder.

30. Multiplexers
 A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it
to a single output line.
 The selection of a particular input line is controlled by a set
of selection lines.
 Normally, there are 2n input lines and n selection lines whose
bit combinations determine which input is selected
 A demultiplexer is a circuit that receives information on a
single line and transmits this information on one of 2n
possible output lines. The selection of a specific output line is
controlled by the bit values of n selection lines.
 o A Decoder with an enable input can function as a
demultiplexer.

32.  Boolean Function implementation
 As decoder can be used to implement a Boolean function
by employing an external OR gate, we can implement any
Boolean function (in SOP) with multiplexer since
multiplexer is essentially a decoder with the OR gate
already available
 Example: Implement Boolean function F(A,B,C)= Σ(1,3,5,6)
with multiplexer.

33. Rom
 A read-only memory (ROM) is a device that includes both
the decoder and the OR gates within a single IC package.
 The connections between the outputs of the decoder and
the inputs of the OR gates can be specified for each
particular configuration.
 32 x 4 ROM (unit consists of 32 words of 8 bits each)
 In this example the input size is 32 so input size will be 5
and output size for variable will be 32 for decoder.

34. Combinational logic
implementation
 Example: Consider a following truth table:
Combinational-circuit
implementation with a
4 x 2 ROM

35. Types of ROM
 1. ROMs
 2. PROM
 3. EPROM
 4. EEPROM
 ROMs: For simple ROMs, mask programming is done by
the manufacturer during the fabrication process of the
unit. The procedure for fabricating a ROM requires that
the customer fill out the truth table the ROM is to satisfy
 This procedure is costly because the vendor charges the
customer a special fee for custom masking a ROM

36.  PROMs: Programmable read-only memory or PROM units
contain all 0's (or all 1's) in every bit of the stored words.
 The approach called field programming is applied for fuses in
the PROM which are blown by application of current pulses
through the output terminals.
 This allows the user to program the unit in the laboratory to
achieve the desired relationship between input addresses and
stored words.
 EPROMs: The hardware procedure for programming ROMs or
PROMs is irreversible and, once programmed, the fixed pattern
is permanent and cannot be altered.
 Once a bit pattern has been established, the unit must be
discarded if the bit pattern is to be changed.
 A third type of unit available is called erasable PROM, or
EPROM. EPROMs can be restructured to the initial value (all 0's
or all 1's) even though they have been changed previously

37.  EEPROMs: Certain ROMs can be erased with electrical signals instead
of ultraviolet light, and these are called electrically erasable PROMs,
or EEPROMs
 The function of a ROM can be interpreted in two different ways:
 The first interpretation is of a unit that implements any combinational
circuit.
 From this point of view, each output terminal is considered separately
as the output of a Boolean function expressed in sum of minterms.
 The second interpretation considers the ROM to be a storage unit
having a fixed pattern of bit strings called words.
 From this point of view, the inputs specify an address to a specific
stored word, which is then applied to the outputs.
 This is the reason why the unit is given the name read-only memory.
Memory is commonly used to designate a storage unit

38. Programmable Logic Array (PLA)
 A combinational circuit may occasionally have don't-care
conditions.
 When implemented with a ROM, a don't care condition
becomes an address input that will never occur.
 The words at the don't-care addresses need not be
programmed and may be left in their original state (all 0's
or all 1's).
 The result is that not all the bit patterns available in the
ROM are used, which may be considered a waste of
available equipment.
 Programmable Logic Array or PLA is LSI component that
can be used in economically as an alternative to ROM
where number of don’t-care conditions is excessive.

39.  PLA diagram consists of n inputs, m outputs, k product
terms, and m sum terms. The product terms constitute a
group of k AND gates and the sum terms constitute a
group of m OR gates. Fuses are inserted between all n
inputs and their complement values to each of the AND
gates. Fuses are also provided between the outputs of
the AND gates and the inputs of the OR gates.